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公开(公告)号：IT201700000532A1
公开(公告)日：2018-07-03
申请号：IT201700000532
申请日：2017-01-03
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , DATI ANGELO , ROTOLO SALVATORE MARIO , BRUCCOLERI MELCHIORRE , FINCATO ANTONIO
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公开(公告)号：ITUB20154605A1
公开(公告)日：2017-04-12
申请号：ITUB20154605
申请日：2015-10-12
Applicant: ST MICROELECTRONICS SRL
Inventor： RADICE FRANCESCO , BRUCCOLERI MELCHIORRE , ZUFFADA MAURIZIO
Abstract: A transimpedance amplifier includes a first and a second power supply terminal for receiving a positive constant supply voltage, wherein the second power supply terminal represents a ground, and an input terminal adapted to be connected to a current source. The transimpedance amplifier further comprises a transistor comprising a control terminal and two further terminals, wherein the input terminal is connected to the control terminal of the first transistor. An inductor is connected between the first of the two further terminals of the transistor and the first power supply terminal, and a bias network is connected between the second of the two further terminals of the transistor and ground. Specifically, the transimpedance amplifier is configured such that the resistance between said first of said two further terminals of said first transistor and said first power supply terminal is small enough, such that said transimpedance amplifier operates as a differentiator.
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公开(公告)号：AT557472T
公开(公告)日：2012-05-15
申请号：AT10179881
申请日：2010-09-27
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , POZZONI MASSIMO
IPC: H03H11/04
Abstract: An architecture of an integrator has an input transconductance amplifier Gi having an output resistance adjustable independently from the transconductance gain Gi, through a dedicated control signal, and includes also a matched transconductance amplifier Gi2 having an adjustable gain and an output resistance matched with that of the first transconductance amplifier Gi and adjusted by the same dedicated control signal. A reference current is forced through the matched output resistance and the dedicated control signal is generated such to keep constant the output voltage of the matched transconductance amplifier. A method of stabilization against PVT variations of the integrated circuit of an integrator is also disclosed.
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公开(公告)号：ITTO20070017A1
公开(公告)日：2008-07-13
申请号：ITTO20070017
申请日：2007-01-12
Applicant: ST MICROELECTRONICS SRL
Inventor： ALBASINI GUIDO GABRIELE , FEDELI MICHELE , ROSSI MATTEO , ZUFFADA MAURIZIO
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Patent Agency Ranking
公开(公告)号：DE69421072T2
公开(公告)日：2000-04-20
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：DE69421072D1
公开(公告)日：1999-11-11
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：DE69421071D1
公开(公告)日：1999-11-11
申请号：DE69421071
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , ALINI ROBERTO
Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.
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公开(公告)号：IT9021816D0
公开(公告)日：1990-10-22
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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公开(公告)号：IT9020728D0
公开(公告)日：1990-06-22
申请号：IT2072890
申请日：1990-06-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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