公开(公告)号：DE102004063531A1

公开(公告)日：2006-07-13

申请号：DE102004063531

申请日：2004-12-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  FISCHER HELMUT

IPC: G11C11/4063

公开(公告)号：DE102004054819B3

公开(公告)日：2006-06-22

申请号：DE102004054819

申请日：2004-11-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTENSCHLAGER RAINER ,  BROX MARTIN ,  HEIN THOMAS ,  MENCZIGAR ULLRICH

IPC: G11C7/10 ,  H04L25/40 ,  H03K19/003

Abstract: The invention creates an electronic circuit arrangement for receiving a received electrical signal ( 101 ) with a first receiving device ( 100 ), a second receiving device ( 200 ) and a comparator unit ( 301 ) for comparing a second signal difference ( 207 ), output by the second receiving device ( 200 ), with a target value signal ( 303 ) and for outputting a control signal ( 305 ) in dependence on the comparison, wherein the control signal ( 305 ) controls both the first receiving device ( 100 ) and the second receiving device ( 200 ) into a respective operating point in such a manner that the amplified second signal difference ( 207 ) is held at a level of the target value signal ( 303 ) and a first signal difference ( 107 ) output from the first receiving device ( 100 ) supplies with high accuracy a measure of the received signal ( 101 ) with respect to a predetermined reference signal ( 103 ).

公开(公告)号：DE69830972T2

公开(公告)日：2006-05-24

申请号：DE69830972

申请日：1998-10-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C11/409 ,  G11C11/41 ,  G11C7/00 ,  G11C7/18 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: The chip has an array of memory cells arranged in rows and columns and each memory cell comprising a pair of bit lines for each column of memory cell. A capacitor (CINT) is provided between paired bit lines and an external capacitor (CEXT) is provided between adjacent bit line pairs. The spacing between paired bit lines is adjusted to be more than spacing between bit lines of each pair.

公开(公告)号：DE102005049204A1

公开(公告)日：2006-05-04

申请号：DE102005049204

申请日：2005-10-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  HOUGHTON RUSSELL J ,  SCHNEIDER HELMUT ,  KIESER-SCHOENIGER SABINE

IPC: G11C11/407

Abstract: A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.

公开(公告)号：DE102004052903A1

公开(公告)日：2006-05-04

申请号：DE102004052903

申请日：2004-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MARKERT MICHAEL ,  PLAN MANFRED ,  SCHROEGMEIER PETER

IPC: G06F13/40 ,  H01L23/528

Abstract: The system has lines with two sections in each case. The sections are connected with each other by repeater and/or buffer mechanisms (101, 102, 103). The repeater and/or mechanism (102) connected with the sections (12a, 12b) are designed as inverted repeater and/or mechanism. The repeater and/or mechanism(101, 103) connected to the sections (11a, 11b, 13a, 13b) is designed as non-inverted repeater and/or mechanism : An independent claim is also included for a method for operating a bus-system.

公开(公告)号：DE102004043050A1

公开(公告)日：2006-04-13

申请号：DE102004043050

申请日：2004-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPIRKL WOLFGANG ,  KILIAN VOLKER ,  KAISER ROBERT ,  BROX MARTIN

IPC: G01R31/3183 ,  G01R31/319 ,  G11C29/48

公开(公告)号：DE10339894B4

公开(公告)日：2006-04-06

申请号：DE10339894

申请日：2003-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C8/12 ,  G11C11/4091

Abstract: The apparatus includes a switch unit for connecting a reader amplifier unit to a bit line or a cell field region and for disconnecting the amplifier from the bit line or cell field region in dependence on the state of a control signal on a control line. The apparatus also has a driver to drive the control signal. An additional switch is provided which can cause a change in state of the control signal applied to the control line. Independent claims also cover a method of operating the apparatus.

公开(公告)号：DE10361724A1

公开(公告)日：2005-08-04

申请号：DE10361724

申请日：2003-12-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G05F1/46 ,  H02M3/135

Abstract: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation system, with a first device for generating an essentially constant voltage from the first voltage, or a voltage derived from it. A further device is provided for generating a further voltage from the first voltage or a voltage derived from it, in particular a voltage which can be higher than the voltage generated by the first device.

公开(公告)号：DE10320792B3

公开(公告)日：2004-10-07

申请号：DE10320792

申请日：2003-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MINZONI ALESSANDRO ,  BROX MARTIN

IPC: G11C7/22 ,  G11C11/4076 ,  H03L7/081 ,  H03L7/087 ,  H03L7/06

Abstract: The clock signal synchronizing arrangement has a first delay device (3) with a variable delay time, a second delay device (8) with a fixed part and a variable part and first (5) and second (9) phase comparison devices whose output signals control the delay time of the first delay device and the delay time of the variable part of the second delay device respectively. An independent claim is also included for the following: (a) a semiconducting memory with an inventive arrangement.

公开(公告)号：DE10249016A1

公开(公告)日：2004-05-06

申请号：DE10249016

申请日：2002-10-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: H03K19/00 ,  H04L25/49 ,  H03F3/16