公开(公告)号：DE10200678A1

公开(公告)日：2003-07-24

申请号：DE10200678

申请日：2002-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENDERS GERHARD

IPC: H01L21/308 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8239

公开(公告)号：DE10131625A1

公开(公告)日：2003-01-23

申请号：DE10131625

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KROENKE MATTHIAS ,  BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L27/105 ,  H01L21/02 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor storage device, in which a semiconductor substrate or similar, a passivation zone (21) and/or a surface zone (20a, 21a) are formed on it with a CMOS structure and in which in the region of the semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) on it are formed a capacitor arrangement (2) of capacitor devices (10-1...10-4) serving as storage elements. At least one part of the capacitor devices (10-1...10-4) are formed with a number of mutually-parallel connected discrete capacitors (C1,C2).

公开(公告)号：DE10105244A1

公开(公告)日：2002-08-22

申请号：DE10105244

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS ,  ENDERS GERHARD

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/108

Abstract: The arrangement has first contact elements (11) arranged in a trench in an insulating material (15) essentially underneath and in electrical contact with lower electrode devices (14) to be contacted using a damascening technique. The first contact elements are isolated by intermediate regions (13) from adjacent condenser devices (10-3) that are not to be contacted. Independent claims are also included for the following: a semiconducting memory device.

公开(公告)号：DE10256973B4

公开(公告)日：2006-09-28

申请号：DE10256973

申请日：2002-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPITZER ANDREAS ,  ENDERS GERHARD

IPC: H01L27/108 ,  G11C11/24 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/12

Abstract: The memory (10) has an array of memory cells (1), each having a memory capacitor (2) and a selection transistor (3) provided on a semiconductor material strut (4) and having 2 source/drain regions (5,6) and at least one gate layer (7,8). The strut is provided on an insulation layer (11) with the source/drain layers at its opposite ends (A,B), the side edges and the upper surface (15) of the strut provided with a gate dielectric layer (9) and a gate electrode layer (16).

公开(公告)号：DE10131492B4

公开(公告)日：2006-09-14

申请号：DE10131492

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  G11C7/00 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

公开(公告)号：DE102004027425A1

公开(公告)日：2005-09-29

申请号：DE102004027425

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOIGT PETER ,  ENDERS GERHARD

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238

Abstract: A process for producing a trench (40) in a layer (14) on the surface of a substrate (10), comprises covering a primary layer section with a mask (16) which has a step at the edge (18). A second material is precipitated on the primary mask structure and on a section not covered by the mask. The second material is then etched, and a second mask structure made of a third material, is applied to the second section next to a spacer. The spacer is then removed by selective etching and the trench is etched in the layer.

公开(公告)号：DE10249650A1

公开(公告)日：2004-05-13

申请号：DE10249650

申请日：2002-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POPP MARTIN ,  ENDERS GERHARD ,  VOIGT PETER

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: The method involves applying gate stacks adjacent to each other to a gate dielectric with a semiconducting substrate of first conductor type with constant sum of common stack width and separation of, determining angle for inclined implantation of first conductor type doping with self-adjustment to gate stack edges, whereby a dose variation compensates for a FET starting voltage variation caused by width variation about desired width. The method involves applying gate stacks adjacent to each other to a gate dielectric (5) with a semiconducting substrate (1) of a first conductor type (p) with a constant sum of a common width (b) and separation (c) of the gate stacks, determining an angle (alpha) for inclined implantation (I) of doping of the first conductor type with self-adjustment to the edges of the gate stacks, whereby a dose variation compensates for a FET starting voltage variation caused by a width variation about a desired width.

公开(公告)号：DE10226583A1

公开(公告)日：2004-01-08

申请号：DE10226583

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: G11C7/00 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

公开(公告)号：DE10131627A1

公开(公告)日：2003-01-30

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: Semiconductor memory has capacitor devices (10-1,...., 10-4) each vertically extending from a substrate (20) and/or a passivating region (21) and/or a surface region (20a). A three dimensional arrangement or structure is formed for each capacitor device. An Independent claim is also included for a process for the production of a semiconductor memory. Preferred Features: The capacitor devices each have a first electrode arrangement (14), a second electrode arrangement (18) with a dielectric (16) arranged between the arrangements. The capacitor devices are a stacked structure of form part of a stacked structure.

公开(公告)号：DE10131624A1

公开(公告)日：2003-01-23

申请号：DE10131624

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/105 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor memory device, in which a semiconductor substrate (20) a passivation zone (21) and/or a surface zone (20a, 21a) are designed with a CMOS structure. The capacitor device (10-1...10-4) is structured mainly in the horizontally-extending semiconductor substrate or similar of a passivation zone (21) and/or a surface zone from it, at least partly and/or locally structured and mainly vertically formed. A passivation zone (21) and/or a surface zone (20a, 21a) is formed and/or structured at least partly in the arrangement or structure extending in the third dimension for the respective capacitor device (10-1...10-4). An Independent claim is given for a chain-FeRAM store. (B)