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    22.
    发明专利
    未知

    公开(公告)号：DE10005619A1

    公开(公告)日：2001-08-30

    申请号：DE10005619

    申请日：2000-02-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  ESTERL ROBERT ,  KANDOLF HELMUT ,  ROEHR THOMAS

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

    24.
    发明专利
    未知

    公开(公告)号：DE10146491B4

    公开(公告)日：2006-04-13

    申请号：DE10146491

    申请日：2001-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KANDOLF HELMUT ,  BRAUN GEORG

    IPC: H04L25/06 ,  H03K19/00 ,  H03K19/0175 ,  H04B3/04 ,  H04L12/40

    Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.

    26.
    发明专利
    未知

    公开(公告)号：DE10017368B4

    公开(公告)日：2005-12-15

    申请号：DE10017368

    申请日：2000-04-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

    IPC: G11C11/22 ,  G11C7/02 ,  G11C7/08 ,  G11C7/22

    Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the "pulsed plate concept". In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

    27.
    发明专利
    未知

    公开(公告)号：DE10328658A1

    公开(公告)日：2005-02-10

    申请号：DE10328658

    申请日：2003-06-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KALMS SVEN ,  KANDOLF HELMUT

    IPC: G06F13/00 ,  G06F13/16

    Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command data have been received in full.

    28.
    发明专利
    未知

    公开(公告)号：DE50104863D1

    公开(公告)日：2005-01-27

    申请号：DE50104863

    申请日：2001-06-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FISCHER HELMUT ,  KANDOLF HELMUT ,  LAMMERS STEFAN

    IPC: G06F11/20 ,  G11C29/00

    Abstract: The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.

    29.
    发明专利
    未知

    公开(公告)号：DE10123593C2

    公开(公告)日：2003-03-27

    申请号：DE10123593

    申请日：2001-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  KANDOLF HELMUT ,  LAMMERS STEFAN

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  G11C11/14

    Abstract: A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

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