公开(公告)号：DE102004005645A1

公开(公告)日：2005-09-22

申请号：DE102004005645

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  LEIBERG WOLFGANG

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

公开(公告)号：DE102004005361A1

公开(公告)日：2005-09-01

申请号：DE102004005361

申请日：2004-02-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO

IPC: H01L21/44 ,  H01L21/60 ,  H01L21/768 ,  H01L51/10 ,  H05K1/09 ,  H05K3/10 ,  H05K3/24 ,  H05K3/40

Abstract: A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from positive resist. The copper core of the interconnects and contact surfaces is surrounded by a nickel-gold layer by means of a second resist mask. The interconnects and contact surfaces are produced by means of two resist masks arranged one on top of the other, in such a way that the copper which forms the core of the interconnect is completely surrounded by the nickel-gold layer, which extends above the copper core, and an adjoining layer that extends beneath the copper core and comprises a diffusion barrier and seed layer.

公开(公告)号：DE10311368A1

公开(公告)日：2003-11-20

申请号：DE10311368

申请日：2003-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBL WERNER ,  BRINTZINGER AXEL ,  FRIESE GERALD ,  GOEBEL THOMAS

IPC: H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L21/28

Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

公开(公告)号：DE10240405A1

公开(公告)日：2003-05-28

申请号：DE10240405

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  BRINTZINGER AXEL ,  WEBER STEFAN

IPC: H01L23/525 ,  H01L21/768 ,  H01L21/8242

Abstract: An antifuse (e.g., 130) is formed in an integrated circuit through the use of a block mask (e.g., photoresist 120) during in situ antifuse dielectric formation. Generally, the mask allows self-aligned oxidation of an oxidizable metal (e.g., aluminum 104) to form the antifuse dielectric (e.g., aluminum oxide 124), while preventing oxidation of non-programmable or fixed connections (e.g., conductive stack 128). The number of mask, deposition, or etching steps may be reduced relative to prior art methods. In addition, a fixed connection may be formed during the formation of and at the same level as the antifuse link.

公开(公告)号：DE60126960T2

公开(公告)日：2007-11-22

申请号：DE60126960

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L23/00 ,  H01L23/58

Abstract: A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.

公开(公告)号：DE69932472T2

公开(公告)日：2007-02-15

申请号：DE69932472

申请日：1999-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  WEBER STEFAN J ,  BRINTZINGER AXEL

IPC: H01L21/768 ,  H01L21/82 ,  H01L23/525

Abstract: A method for forming a semiconductor integrated circuit having a fuse and an active device. A dielectric layer is formed over the fuse and over a contract region of the active device. Via holes are formed through selected regions of the dielectric layer exposing underlying portions of the fuse and underlying portions of a contact region of the active device. An electrically conductive material is deposited over the dielectric layer and through the via holes onto exposed portions of the fuse and the contact region. Portions of the electrically conductive material deposited onto the fuse are selectively removed while leaving portions of the electrically conductive material deposited onto the contact region of the active device. A fill material is disposed in the one of the fuse, a bottom portion of such filling material being spaced from the fuse.

公开(公告)号：DE102004005645B4

公开(公告)日：2006-01-12

申请号：DE102004005645

申请日：2004-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  LEIBERG WOLFGANG

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

公开(公告)号：DE10356119B3

公开(公告)日：2005-08-18

申请号：DE10356119

申请日：2003-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  RUCKMICH STEFAN ,  TROVARELLI OCTAVIO

IPC: H01L21/4763 ,  H01L21/60 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

Abstract: An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.

公开(公告)号：DE10258093B3

公开(公告)日：2004-08-26

申请号：DE10258093

申请日：2002-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/50

Abstract: An electronic component includes a wafer and a number of bond pads disposed on the wafer. A number of functional 3-D structures are disposed on the wafer. Each functional 3-D structure includes a compliant base element. A number of reroute traces are electrically connected to one of the bond pads and extend onto a surface of one of the functional 3-D structures. A number of selected 3-D structures is disposed on the wafer to provide a mechanical reinforcement. At least some of the selected 3-D structures have a greater mechanical load-bearing capacity than some the functional 3-D structures.

公开(公告)号：DE10156054A1

公开(公告)日：2003-05-28

申请号：DE10156054

申请日：2001-11-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL

IPC: H01L23/52 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485

Abstract: Method for fabricating an interconnect on a substrate. The method includes applying a mask on the substrate, patterning the mask, so that it has an opening corresponding to the interconnect, providing the interconnect in the opening on the substrate, widening the opening in order to uncover a region laterally adjoining the interconnect, encapsulating of interconnect in the widened opening, andremoving the mask.