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    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR
    21.
    发明专利
    METHOD FOR MANUFACTURING VERTICAL BIPOLAR TRANSISTOR 失效

    公开(公告)号：JP2001196385A

    公开(公告)日：2001-07-19

    申请号：JP2000353964

    申请日：2000-11-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To propose a vertical bipolar transistor which has a reduced low-frequency noise and allowable static parameters. SOLUTION: This vertical bipolar transistor includes an intrinsic collector 4 on an extrinsic collector layer 2 buried in a semiconductor substrate, a side separation area 5 surrounding the upper part of the intrinsic collector 4, an offset extrinsic collector well 60, a base 8 which is arranged on the intrinsic collector 4 and side separation area 5 and is composed of a semiconductor area including at least one silicon layer, and two doped emitters 11 surrounded with the base 8. The emitters 11 include a first part 110 which is made of single crystal and is directly in contact with the upper surface in the predetermined window 800, and a second part 111 formed of polycrystal. These two parts are isolated by an isolated oxide layer 112 arranged at an optional distance apart from an emitter base joint part.

    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF
    22.
    发明专利
    LOW NOISE VERTICAL BIPOLAR TRANSISTOR AND FABRICATION THEREOF 失效

    公开(公告)号：JP2000031155A

    公开(公告)日：2000-01-28

    申请号：JP15604999

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To reduce low frequency noise while sustaining accurate current amplification factor by obtaining an emitter region of single crystal silicon touching the upper layer of a stack, e.g. silicon of an upper encapsulation layer of the stack, directly on a window. SOLUTION: On a silicon substrate 1, a buried extrinsic collector layer 2 doped with n+ by implanting arsenic and two buried layers 3 similarly doped with p+ are formed and a thick n-type single crystal silicon layer 4 is grown epitaxially. Subsequently, an amorphous silicon layer 17 is deposited on a semiconductor block thus formed and etched above an oxide layer 6 to form a window 170 which is then subjected to desorption. Thereafter, a stack 8 is formed, a silicon dioxide layer 9 and a silicon nitride layer 10 are deposited thereon and then the layers 9, 10 are removed from a desired zone to obtain an emitter, i.e., an emitter window 800.

    METHOD FOR SELECTIVELY DOPING INTRINSIC COLLECTOR OF VERTICAL BIPOLAR TRANSISTOR HAVING EPITAXIAL BASE
    23.
    发明专利
    METHOD FOR SELECTIVELY DOPING INTRINSIC COLLECTOR OF VERTICAL BIPOLAR TRANSISTOR HAVING EPITAXIAL BASE 失效

    公开(公告)号：JPH11354537A

    公开(公告)日：1999-12-24

    申请号：JP15606599

    申请日：1999-06-03

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  SCHARY SCHWARZMANN

    IPC: H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To increase the operating speed of a transistor, by executing the injection of a first dopant into the intrinsic collector of the transistor before nonselective epitaxy and the injection of a second dopant into the inner part of the collector at a smaller injected amount and with lower energy than the first dopant through an epitaxially grown stack. SOLUTION: The operating speed of a transistor is the value of the frequency (cut-off frequency of the current amplification factor) of the transistor and the value of the maximum oscillation frequency. The injection of a first dopant into an intrinsic collector 4 in a silicon substrate 1 is executed before the formation of a stack 8 which is formed in an intrinsic base and this injection is high- energy injection. The injection of a second dopant into the collector 4 is executed through an epitaxial base and the injected amount of the second dopant is 1/10 as small as that of the first dopant. Therefore, the defect level in the stack 8 becomes very low and, as a result, a thinner intrinsic base can be obtained and the speed of the transistor increases accordingly.

    DEEP INSULATING TRENCH AND METHOD FOR PRODUCTION THEREOF
    24.
    发明申请
    DEEP INSULATING TRENCH AND METHOD FOR PRODUCTION THEREOF 审中-公开
    深层绝缘固化剂及其生产方法

    公开(公告)号：WO02103772A2

    公开(公告)日：2002-12-27

    申请号：PCT/FR0202029

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV ,  MARTY MICHEL ,  FORTUIN ARNOUD ,  ARNAL VINCENT

    Inventor： MARTY MICHEL ,  FORTUIN ARNOUD ,  ARNAL VINCENT

    IPC: H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764

    CPC classification number: H01L21/76232 ,  H01L21/31612 ,  H01L21/76237 ,  H01L21/764

    Abstract: The invention relates to a deep insulating trench, comprising side walls (11) and a base (10), embodied in a semiconductor substrate (1). The side walls (11) and the base (10) are coated with an electrically insulating material (12) which defines an empty cavity (13) and forms a plug (14) to seal the cavity (13). The side walls (11) are embodied with a neck (15) for determining the position of the plug (15) and a first section (16) which tapers out towards the neck (15) with increasing separation from the base (10). The above is particularly suitable for application in bipolar circuits and BiCMOS.

    Abstract translation: 本发明涉及一种深绝缘沟槽，包括实施在半导体衬底（1）中的侧壁（11）和底座（10）。 侧壁（11）和基座（10）涂覆有限定空腔（13）并形成密封空腔（13）的塞子（14）的电绝缘材料（12）。 侧壁（11）具有用于确定插头（15）的位置的颈部（15）和与基部（10）分离的方式朝向颈部（15）逐渐变细的第一部分（16）。 以上特别适用于双极电路和BiCMOS。

    28.
    发明专利
    未知

    公开(公告)号：DE60025456D1

    公开(公告)日：2006-04-06

    申请号：DE60025456

    申请日：2000-09-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HOMEGALPINE

    IPC: H01L21/00 ,  H01L29/73 ,  H01L21/205 ,  H01L21/22 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

    Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

    29.
    发明专利
    未知

    公开(公告)号：FR2848724B1

    公开(公告)日：2005-04-15

    申请号：FR0215837

    申请日：2002-12-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

    IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

    Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

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