公开(公告)号：DE60307475T2

公开(公告)日：2007-03-29

申请号：DE60307475

申请日：2003-10-21

Applicant: ST MICROELECTRONICS SRL

Inventor： SERGIO MAXIMILIAN ,  MANARESI NICOLO ,  TARTAGNI MARCO ,  GUERRIERI ROBERTO ,  CANEGALLO ROBERTO

IPC: G01R27/02 ,  B60C23/06 ,  G01M17/02

Abstract: The present invention refers to a method for the determination of the physical features of a tire, for example the deformations that it undergoes during the use.The method for the determination of the physical features of a tire, comprises at least a first belt (3,4) reinforced with a plurality of metallic wires, characterized by comprising the following phases: providing a signal between a first and a second metallic wire; determining the real part and the imaginary part of the impedance between said first metallic wire and said second metallic wire.

公开(公告)号：DE60027706D1

公开(公告)日：2006-06-08

申请号：DE60027706

申请日：2000-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： ZANUCCOLI MAURO ,  CANEGALLO ROBERTO ,  DOZZA DAVIDE

IPC: H02M3/07

Abstract: The load pump booster device (1) with transfer and recovery of the charge comprises a charge pump circuit (2) with an output terminal (30.N) which is connected to a load capacitor (12) by means of a load node (50). In turn, the charge pump circuit (2) comprises a plurality of transfer transistors (15.0, ..., 15.j, ..., 15.N) which are connected to one another in series, and define a plurality of transfer nodes (30.0, ..., 30.j, ..., 30.N). Each transfer node (30.0, ..., 30.j, ..., 30.N) is connected to a storage capacitor (14.0, ..., 14.j, ..., 14.N). The booster device (1) also comprises a plurality of controlled switches (40.0, ..., 40.j, ..., 40.N) which are interposed between the said load node (50) and a respective transfer node (30.0, ..., 30.j, ..., 30.N), in order to connect to the said load node (50) a single one of the said transfer nodes (30.0, ..., 30.j, ..., 30.N). By this means, between the load capacitor (12) and the storage capacitors (14.0, ..., 14.j, ..., 14.N) there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors (14.0, ..., 14.j, ..., 14.N) to the load capacitor (12).

公开(公告)号：DE69824386D1

公开(公告)日：2004-07-15

申请号：DE69824386

申请日：1998-01-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  CHIOFFI ERNESTINA ,  GUAITINI GIOVANNI ,  LHERMET FRANK ,  ROLANDI PIERLUIGI

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00 ,  G11C16/06

公开(公告)号：DE69629029T2

公开(公告)日：2004-06-03

申请号：DE69629029

申请日：1996-12-05

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

IPC: G11C29/00

公开(公告)号：IT1313199B1

公开(公告)日：2002-06-17

申请号：ITMI991618

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： DOZZA DAVIDE ,  CANEGALLO ROBERTO ,  BORGATTI MICHELE

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

公开(公告)号：ITTO20000146A1

公开(公告)日：2001-08-16

申请号：ITTO20000146

申请日：2000-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： ZANUCCOLI MAURO ,  CANEGALLO ROBERTO ,  DOZZA DAVIDE

IPC: H02M3/07

Abstract: A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together. Each voltage boosting stage is connected to the adjacent stages via a first transfer node and a second transfer node and includes a storage capacitor connected at a terminal thereof to the second transfer node and receiving on the other terminal a first phase signal switching between a first value and a second value; a switch element including an NMOS transistor connected between the first transfer node and the second transfer node; a voltage boosting capacitor connected at a terminal thereof to the control terminal of the switch element and receiving on the other terminal a second phase signal; a first precharge circuit connected between the first transfer node and the control terminal of the switch element so as to control charge transfer from the first transfer node to the second transfer node when activated by a first activation signal; and a second precharge circuit connected between the second transfer node and the control terminal of the switch element so as to control charge transfer from the second transfer node to the first transfer node when activated by a second activation signal. The first activation signal and second activation signal are never active simultaneously.

公开(公告)号：ITMI991618A1

公开(公告)日：2001-01-22

申请号：ITMI991618

申请日：1999-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： DOZZA DAVIDE ,  CANEGALLO ROBERTO ,  BORGATTI MICHELE

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

公开(公告)号：ITMI982787A1

公开(公告)日：2000-06-22

申请号：ITMI982787

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  GUAITINI GIOVANNI ,  ROLANDI PIERLUIGI

IPC: G05F1/565

公开(公告)号：ITTO20101079A1

公开(公告)日：2012-06-30

申请号：ITTO20101079

申请日：2010-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CANEGALLO ROBERTO ,  SCANDIUZZO MAURO

公开(公告)号：DE69833178D1

公开(公告)日：2006-04-06

申请号：DE69833178

申请日：1998-10-20

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

IPC: G11C27/00 ,  G11C11/56 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34

Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.