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    21.
    发明专利
    未知

    公开(公告)号：DE69824143D1

    公开(公告)日：2004-07-01

    申请号：DE69824143

    申请日：1998-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARCHESE STEFANO ,  PISATI VALERIO ,  PORTALURI SALVATORE ,  SAVO ALESSANDRO

    IPC: H03G1/00 ,  H03G7/06 ,  H03G3/00 ,  H03G7/00

    Abstract: An amplifier with programmable gain and input linearity, comprising an input stage (10), which is suitable to receive a voltage signal (V , V ) and perform current conversion thereof with compression, and an output stage (30), which is connected to the input stage (10) and is suitable to decompress the signal in output from the input stage, producing gain amplification thereof; the particularity of the amplifier is the fact that it further comprises at least one current amplifier stage (20) which is interposed between the input stage (10) and the output stage (30) and comprises at least one bipolar transistor (21, 22) which is series-connected to a load diode (23, 24) and to a current source (2I2); programmable means (I2, I2*) for reducing the transconductance of the load diode (23, 24) being provided in the at least one amplifier stage (20) to determine a programmable amplification factor for the gain of the amplifier.

    22.
    发明专利
    未知

    公开(公告)号：DE69426776D1

    公开(公告)日：2001-04-05

    申请号：DE69426776

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PORTALURI SALVATORE

    IPC: G06G7/16 ,  G06G7/163

    Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.

    23.
    发明专利
    未知

    公开(公告)号：DE69519663D1

    公开(公告)日：2001-01-25

    申请号：DE69519663

    申请日：1995-03-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  VAI GIANFRANCO ,  PORTALURI SALVATORE ,  DEMICHELI MARCO

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

    Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.

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