中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.02 seconds)

    21.
    发明专利
    未知

    公开(公告)号：IT1303201B1

    公开(公告)日：2000-10-30

    申请号：ITTO980990

    申请日：1998-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

    22.
    发明专利
    未知

    公开(公告)号：ITMI20000832D0

    公开(公告)日：2000-04-13

    申请号：ITMI20000832

    申请日：2000-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI ,  ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  PASOTTI MARCO

    IPC: G01R31/28

    Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

    23.
    发明专利
    未知

    公开(公告)号：ITTO990944D0

    公开(公告)日：1999-10-29

    申请号：ITTO990944

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C11/56 ,  G11C16/28

    Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

    26.
    发明专利
    未知

    公开(公告)号：DE69628165D1

    公开(公告)日：2003-06-18

    申请号：DE69628165

    申请日：1996-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  LEONG PHILIP ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

    IPC: H03M1/74

    Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

    28.
    发明专利
    未知

    公开(公告)号：IT1317248B1

    公开(公告)日：2003-05-27

    申请号：ITMI20000832

    申请日：2000-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  GUAITINI GIOVANNI ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI

    IPC: G01R31/28

    Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

    29.
    发明专利
    未知

    公开(公告)号：IT1308857B1

    公开(公告)日：2002-01-11

    申请号：ITTO990944

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C11/56 ,  G11C16/28

    Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

    30.
    发明专利
    未知

    公开(公告)号：IT1308855B1

    公开(公告)日：2002-01-11

    申请号：ITTO990942

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI

    IPC: G11C16/12

    Abstract: A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line. The method includes supplying at least one soft programming pulse to the plurality of memory cells for a time interval. In this step, a bulk voltage with a rising negative ramp is applied to the common bulk line for the time interval. By this means, the threshold voltage of the cells is increased by body effect, and initially only the most depleted cells are soft programmed, with a limited drain current. Subsequently, when the bulk voltage increases, the cells with a higher threshold voltage are also soft programmed, until all the cells have reached the required minimum threshold value.

Patent Agency Ranking