公开(公告)号：ITMI971333A1

公开(公告)日：1998-12-07

申请号：ITMI971333

申请日：1997-06-05

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： SIRNA GUGLIELMO ,  PALMISANO GIUSEPPE ,  PAPARO MARIO

IPC: H03K19/018

公开(公告)号：DE69126618T2

公开(公告)日：1998-01-08

申请号：DE69126618

申请日：1991-11-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).

公开(公告)号：DE69126618D1

公开(公告)日：1997-07-24

申请号：DE69126618

申请日：1991-11-25

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).

公开(公告)号：IT9022577A1

公开(公告)日：1992-07-01

申请号：IT2257790

申请日：1990-12-31

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PUZZOLO SANTO ,  ZAMBRANO RAFFAELE

IPC: H01L21/8249 ,  H01L20060101 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

公开(公告)号：DE69032552D1

公开(公告)日：1998-09-17

申请号：DE69032552

申请日：1990-10-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PALARA SERGIO ,  PAPARO MARIO ,  PELLICANO' ROBERTO

IPC: G05F1/56 ,  G05F3/22 ,  G05F1/10 ,  H01F7/18 ,  H03K17/16 ,  H03K17/615

Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

公开(公告)号：IT1236627B

公开(公告)日：1993-03-25

申请号：IT2210489

申请日：1989-10-24

Applicant: ST MICROELECTRONICS SRL

Inventor： PALARA SERGIO ,  PAPARO MARIO ,  PELLICANO' ROBERTO

IPC: G05F1/56 ,  G05F3/22 ,  G05F1/10 ,  H01F7/18 ,  H03K17/16 ,  H03K17/615 ,  H02H ,  H01L

Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

公开(公告)号：ITMI20111896A1

公开(公告)日：2013-04-20

申请号：ITMI20111896

申请日：2011-10-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PAPARO MARIO ,  PATTI DAVIDE GIUSEPPE ,  ROSSI DOMENICO

公开(公告)号：DE102014005866A1

公开(公告)日：2014-11-13

申请号：DE102014005866

申请日：2014-04-23

Applicant: ST MICROELECTRONICS SRL

Inventor： PATTI DAVIDE GIUSEPPE ,  PAPARO MARIO

IPC: F02P17/00

Abstract: Der Druck in dem Brennraum eines elektronisch gesteuerten Motors mit Zündkerzenzündung kann ohne spezielle Sensoren im Echtzeitmodus geschätzt werden, indem erfasste Ionisationsstromdaten verarbeitet werden, um Merkmale der Stromwellenform zu berechnen, die nachgewiesenerweise mit dem Druck innerhalb des Motorzylinders korrelieren, und diese auf der Grundlage einer Nachschlagetabelle von zeitinvarianten Korrelationskoeffizienten, die durch eine Kalibrierungskampagne von Tests an einem gezielt mit Sensoren ausrüsteteten Testmotor erzeugt werden, in Korrelation zu setzen. Ein mathematisches Modell des elektrischen und physischen Zündkerzenzündungssystems und des Brennraums des Motors wird während der Kalibrierung durch wiederholtes Testen der interaktiven Leistung von Korrelationskoeffizienten von zugehörigen Termen eines mathematischen Ausdrucks des Modells und Vergleichen des ausgedrückten Druckwerts mit dem tatsächlichen Druckwert, wie von einem Sensor gemessen, verfeinert. Die erzeugte Nachschlagetabelle und das verfeinerte Modell sind in ein fahrzeugeigenes System eingebettet, das den Ionisationsstrom in dem laufenden Motor erfasst, mindestens eines oder mehrere wesentliche Merkmale der Wellenform des erfassten Ionisationsstroms misst oder berechnet und einen oder mehrere der gemessenen oder berechneten Merkmalswerte zusammen mit der Matrix von zeitinvarianten Koeffizienten und mit einem Satz von tatsächlichen Werten der Parameter außer dem Druck und/oder der Steuereinstellungen des laufenden Motors verarbeitet, um einen ausgewerteten Wert des Brennraumdrucks zu erzeugen. Ausführungsformen des Kalibrierungsprozesses und von Echtzeiterfassung von Ionenstromdaten, analoges Filtern, A/D-Umwandlung und Schätzung des Drucks (CCP) sind offenbart.

公开(公告)号：DE69927004D1

公开(公告)日：2005-10-06

申请号：DE69927004

申请日：1999-06-16

Applicant: ST MICROELECTRONICS SRL

Inventor： CALI GIOVANNI ,  PAPARO MARIO ,  PELLERITI ROBERTO

IPC: G05F1/575

Abstract: The invention relates to a low-drop type of voltage regulator (1) formed with BiCMOS/CMOS technology and being of the type which comprises: an input terminal (IN), receiving a stable voltage reference (Vrif) and being connected to one input (-) of an operational amplifier (2) through a switch controlled by a power-on enable signal (CE); a supply voltage reference (Vpos) powering the operational amplifier (2); an output transistor (M1) connected to an output (U) of the amplifier (2) to generate a regulated voltage value (Vreg) to be fed back to the amplifier (2) input; a second transistor (M2) connected in series between the output transistor (M1) and the supply voltage reference (Vpos). The regulator of this invention comprises a control circuit portion (7) connected between the control terminal of the second transistor (M2) and the supply voltage reference (Vpos) to prevent the breakdown of the output transistor (M1) from occurring.

公开(公告)号：IT1251097B

公开(公告)日：1995-05-04

申请号：ITMI912045

申请日：1991-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： ZISA MICHELE ,  BELLUSO MASSIMILIANO ,  PAPARO MARIO

IPC: H03K4/58 ,  H03F3/217 ,  H03K5/02 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017 ,  H03K

Abstract: In a bootstrap circuit for a power MOS transistor in the high driver configuration, comprising a first capacitor (C1) chargeable to a first voltage function of the supply voltage of the power transistor (T1), there is present a second capacitor (C2) combined with the first capacitor (C1) in such a way as to make available a second voltage higher than the first voltage and the threshold voltage of the power transistor (T1).