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    Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors
    21.
    发明公开
    Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more different sectors 有权
    架构是闪速EEPROM，而擦除或一个或多个其它扇区的编程，读取同一时间。

    公开(公告)号：EP1327992A1

    公开(公告)日：2003-07-16

    申请号：EP02425009.4

    申请日：2002-01-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Silvagni, Andrea ,  Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C16/08 ,  G11C8/16

    CPC classification number: G11C16/08 ,  G11C2216/22

    Abstract: A non volatile memory device based on the realization of two distinct orders of main wordlines and bitlines, distinguishing a first order as main read wordlines (MWLR) and main read bitlines (MBLR) and a second order as main program wordlines (MWLP) and main program bitlines (MBLP), to each pair of main lines of which are associated a certain number of local lines, for example four lines, in each sector of subdivision of the array of memory cells, according to the criteria that are normally used in the so called hierarchical decoding structures of a memory whose array of elementary memory cells is subdivided in banks and/or sectors.
    Distinct decoders are associated to the two distinct orders of main wordlines and of main bitlines, the relative inputs of which are two address buses for reading and programming/erasing operations, respectively. A first address bus (RADD) coming from the address input pads of the device, through commonly used circuits, realizes a path for the read addresses to be input to main read wordlines decoders and to main read bitlines decoders. The input of the decoders of the main program wordlines and of the main program bitlines is, on the contrary, provided by an internal bus (PADD), generated by controllers of program and erase operations that control all the verification and load operations of data to be programmed.

    Abstract translation: 基础上，实现主字线和位线的两个不同的订单的非易失性存储器装置中，区分第一顺序作为主要的读字线（MWLR）和主读出的位线（MBLR）和第二顺序主程序字线（MWLP）和主 其中的程序位线（MBLP）到每对的主线相关联的本地线路一定数量，例如四个行存储器单元的阵列的细分的每个扇区，雅鼎的准则并通常在所使用的 所谓的初级的存储器数组，其存储单元是细分在银行和/或扇区的层次解码处理的结构。 不同的解码器关联到主字线和主位线的两个不同的订单，其中的相对输入是两个地址总线用于读取和编程/擦除分别操作，。 第一地址总线（RADD）从装置的地址输入焊盘来，通过通常使用的电路中，实现了路径的读出地址将被输入到主读出字线和解码器到主读位线解码器。 节目字的主线和主程序位线的解码器的输入是，与此相反，通过内部总线上提供（PADD），通过程序的控制器产生和擦除操作做了控制的所有数据的验证和装载操作，以 进行编程。

    Method and circuit for timing dynamic reading of a memory cell with control of the integration time
    23.
    发明公开
    Method and circuit for timing dynamic reading of a memory cell with control of the integration time 有权
    方法和电路，其与该积分时间的控制定时的存储器单元的动态读

    公开(公告)号：EP1251523A1

    公开(公告)日：2002-10-23

    申请号：EP01830266.1

    申请日：2001-04-19

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56 ,  G11C7/22 ,  G11C16/28 ,  G11C16/32

    CPC classification number: G11C7/062 ,  G11C7/04 ,  G11C7/22 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/063 ,  G11C2211/5634

    Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (10) with a constant current (I) by means of a first capacitive element (23), integrating said current (I) in a time interval (Δt), and controlling the duration of the time interval (Δt) in such a way as to compensate for any deviations in the current (I) from a nominal value. In particular, a reference current (I R ) is supplied to a reference cell (101) by means of a second capacitive element (122); next, a first voltage (Var) present on the second capacitive element (122) is measured; finally, the memory cell (10) is deactivated when the first voltage (Var) is equal to a second voltage (Vref), which is constant.

    Abstract translation: 用于定时的存储器单元的读出的方法，设想供给由第一电容性元件（23）的装置中的存储单元（10）以恒定电流（I），INTEGRA挺表示当前在时间间隔（I）（DELTA t）的 并在寻求一种方式从一个标称值的电流（I）以补偿任何偏差控制的时间间隔（DELTA t）的持续时间。 特别地，参考电流（IR）由第二电容性元件（122）的装置提供到参考单元（101）; 下，第一电压（VAR）存在于所述第二电容元件（122）上被测量; 最后，存储单元（10）被去激活时，第一电压（VAR）是等于第二电压（V REF），所有这些是恒定的。

    Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics
    25.
    发明公开
    Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics 有权
    在低电源电压和用小的输出动态的方法和电路用于存储单元的动态读

    公开(公告)号：EP1233420A1

    公开(公告)日：2002-08-21

    申请号：EP01830097.0

    申请日：2001-02-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C11/56 ,  G11C16/26 ,  G11C7/06

    CPC classification number: G11C11/565 ,  G11C7/06 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

    Abstract: The method for reading a memory cell includes supplying the cell (30) with a first charge quantity (ΔQb) through a capacitive integration element (39) and reintegrating the first charge quantity (ΔQb) through a plurality of second charge quantities (Qa) supplied alternately and in succession to the capacitive integration element (39). In a first embodiment, the second charge quantities (Qa) are initially stored in a plurality of capacitive charge-regeneration elements (37, 38) connected alternately and in succession to the capacitive integration element (39); the second charge quantities (Qa) are then shared between the capacitive integration element (39) and the capacitive charge-regeneration elements (37, 38).

    Abstract translation: 用于读取存储器单元的方法，包括：通过电容积分元件（39）供给用的第一电荷量（DELTA Qb）大的电池（30），并且通过第二电荷量一个多元化重返第一批数量（DELTA Qb）大（QA ）提供可替换地和（连续到电容积分元件39）。 在第一实施例，第二批量（QA）在电容充再生元件的多元性最初被存储（37，38）交替连接和连续到所述电容积分元件（39）; 第二电荷量（Q），然后在电容元件集成（39）和所述电容性电荷再生单元（37,38）之间共享。

    Nonvolatile memory device, having parts with different access time, reliability and capacity
    26.
    发明公开
    Nonvolatile memory device, having parts with different access time, reliability and capacity 审中-公开
    具有不同的可靠性，访问时间和容量份的非易失性存储器设备

    公开(公告)号：EP1193715A1

    公开(公告)日：2002-04-03

    申请号：EP00830627.6

    申请日：2000-09-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni

    IPC: G11C11/56 ,  G11C16/04

    CPC classification number: G11C11/5621 ,  G11C16/0416 ,  G11C2211/5641

    Abstract: The multilevel memory device (1) has a memory section containing cells (2a) that can be programmed with a predetermined number of levels greater than two, i.e. a multilevel array (2), and a memory section containing cells that can be programmed with two levels, i.e. a bilevel array (3). The multilevel array (2) is used for storing high density data, for which speed and reliability of reading are not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array (3) is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device (1), are common to both arrays.

    Abstract translation: 多级存储器装置（1）具有一个存储器部分包含（2a）中那样细胞可以用预定数量的水平的大于二，即，被编程 多级阵列（2），和包含细胞的存储部并可以与两个级别，即进行编程 一个双层阵列（3）。 所述多级阵列（2）用于存储高密度数据，为此，速度和读出可靠性不是必需的，例如用于存放系统包括存储器装置的操作的代码。 在另一方面，所述双层阵列（3）是一种用于存储数据用于哪个高速和读取可靠性是至关重要的，：诸如个人计算机的BIOS，并且将数据存储在高速缓冲存储器。 所必需的存储器设备（1）的手术专用于编程，测试指令写入的电路部分，并且所有的功能，是共同的阵列。

    Nonvolatile memory device, in particular of flash type
    28.
    发明公开
    Nonvolatile memory device, in particular of flash type 有权
    NichtflüchtigeSpeicheranordnung，insbesondere vom Flash-Typ

    公开(公告)号：EP1063653A1

    公开(公告)日：2000-12-27

    申请号：EP99830396.0

    申请日：1999-06-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Zammattio, Matteo ,  Campardo, Giovanni

    IPC: G11C16/16 ,  G11C16/08

    CPC classification number: G11C8/12 ,  G11C16/12

    Abstract: The memory device (21) has hierarchical sector decoding (24, 25). A plurality of groups of supply lines (28-32) is provided, one for each sector row, extending parallel to the sector rows. A plurality of switching stages (35) are each connected between a respective sector (15) and a respective group of supply lines (28-32); the switching stages (35) connected to sectors (15) arranged on a same column are controlled by same control signals (S0, S1) supplied on control lines (40) extending parallel to the columns of sectors. For biasing the sectors, modification voltages (NW, SB, V NEG ) are sent to at least one selected group of biasing lines (28-32), and control signals (SO, S1) are sent to the switching stages connected to a selected sector column.

    Abstract translation: 存储器件（21）具有分级扇区解码（24,25）。 提供多组供应线（28-32），每个扇区行一个平行于扇区行延伸。 多个开关级（35）分别连接在相应的扇区（15）和相应的一组供电线（28-32）之间。 连接到布置在同一列上的扇区（15）的开关级（35）由与扇区列平行延伸的控制线（40）上提供的相同控制信号（S0，S1）控制。 为了偏置扇区，将修改电压（NW，SB，VNEG）发送到至少一组选定的偏置线（28-32），并且控制信号（SO，S1）被发送到连接到所选扇区的开关级 柱。

    Memory circuit with improved address signal generator
    29.
    发明公开
    Memory circuit with improved address signal generator 失效
    Speicherschaltung mit verbicultem Adressensignalgenerator

    公开(公告)号：EP0913829A1

    公开(公告)日：1999-05-06

    申请号：EP97830558.9

    申请日：1997-10-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Commodaro, Stefano ,  Ghezzi, Stefano ,  Maccarrone, Marco

    IPC: G11C8/04 ,  G11C16/06

    CPC classification number: G11C16/16 ,  G11C8/04

    Abstract: The present invention relates to a semiconductor memory device with an improved address signal generator. The memory device comprises an array of memory elements (10), first decoding circuit means (8,15) for decoding a first set of address signals (7,14) for the selection of said memory elements, and second circuit means (4) for the generation internally to the memory of a sequence of values for said address signals (3,11). The second circuit means (4) generates said sequence so that successive values in the sequence differ for the logic state of only one of said address signals (3,11).

    Abstract translation: 本发明涉及具有改进的地址信号发生器的半导体存储器件。 存储器件包括存储元件阵列（10），第一解码电路装置（8,15），用于对用于选择所述存储器元件的第一组地址信号（7,14）进行解码;以及第二电路装置（4） 用于内部生成用于所述地址信号（3,11）的一系列值的存储。 第二电路装置（4）产生所述序列，使得序列中的连续值对于仅一个所述地址信号（3,11）的逻辑状态不同。

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