公开(公告)号：EP1873821A1

公开(公告)日：2008-01-02

申请号：EP06116123.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method for manufacturing an integrated electronic device (100;400;500) is proposed. The method comprises the steps of: providing an SOI substrate (105;505) comprising a semiconductor substrate (110;510), an insulating layer (115;515) on the semiconductor substrate, and a semiconductor starting layer (112;512) on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer (142;542) on the insulating layer for integrating components of the device, and forming at least one contact trench (120;520) extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion (130b,130s;530b,530s) of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract translation: 提出了一种用于制造集成电子装置（100; 400; 500）的方法。 该方法包括以下步骤：提供包括半导体衬底（110; 510），半导体衬底上的绝缘层（115; 515）和半导体起始层（112; 512）上的SOI衬底（105; 505） 绝缘层; 外延生长所述起始层以在所述绝缘层上获得半导体有源层（142; 542），用于对所述器件的部件进行积分，以及形成从所述起始层的暴露表面延伸到所述至少一个接触沟槽（120; 520） 在外延生长起始层的步骤之前的半导体衬底，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的对应部分（130b，130s; 530b，530s），外延生长被进一步应用 到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：EP1028466B1

公开(公告)日：2006-08-02

申请号：EP99830068.5

申请日：1999-02-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Castoldi, Laura ,  Ferrera, Marco

IPC: H01L27/00 ,  G01P1/00 ,  B81B3/00

CPC classification number: B81B3/0072 ,  B81B2203/033 ,  B81C1/00666 ,  B81C2201/017 ,  G01P15/0802 ,  G01P2015/0828

公开(公告)号：EP1028466A1

公开(公告)日：2000-08-16

申请号：EP99830068.5

申请日：1999-02-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Castoldi, Laura ,  Ferrera, Marco

IPC: H01L27/00 ,  G01P1/00

CPC classification number: B81B3/0072 ,  B81B2203/033 ,  B81C1/00666 ,  B81C2201/017 ,  G01P15/0802 ,  G01P2015/0828

Abstract: On a substrate (20) of semiconductor material, a sacrificial region (21) is formed and an epitaxial layer (25) is grown; then a stress release trench (31) is formed, surrounding an area (33) of the epitaxial layer (25), where an integrated electromechanical microstructure is to be formed; the wafer (28) is then heat treated, to release residual stress. Subsequently, the stress release trench (31) is filled with a sealing region (34) of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region (34), a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

Abstract translation: 上的半导体材料的基片（20），牺牲区域（21）被形成和外延层（25）上生长; 外延层（25），其中，在集成式机电微观结构是将要形成的那么应力释放槽（31）形成，周边区域（33）; 晶片（28）进行热处理，以释放残余应力。 接着，应力释放槽（31）中填充有电介质材料制成的密封区域（34），和集成的部件而形成。 最后，通过密封区域（34）包围的区域内，微结构定义沟槽中形成，并且所述牺牲区域被去除，因此，与零张残余应力获得集成微结构。

公开(公告)号：EP0922944A3

公开(公告)日：1999-11-10

申请号：EP98830266.7

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

IPC: G01L9/00

CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

公开(公告)号：EP0890978A1

公开(公告)日：1999-01-13

申请号：EP97830345.1

申请日：1997-07-10

Applicant: STMicroelectronics S.r.l.

Inventor： Vigna, Benedetto ,  Ferrari, Paolo ,  Ferrera, Marco ,  Montanini, Pietro

IPC: H01L21/00 ,  G01P15/00 ,  G01C19/00

CPC classification number: H01L21/764 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2203/0307 ,  B81C1/00246 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0735 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/76202

Abstract: To increase the sensitivity of the sensor the suspended structure (40) forming the seismic mass has a tungsten core (26) which has high density. To manufacture it, a sacrificial layer (21) of silicon oxide, a polycrystal silicon layer (24), a tungsten layer (26) and a silicon carbide layer (28) are deposited in succession over a single crystal silicon body (1); the suspended structure (40) is defined by selectively removing the silicon carbide (28), tungsten (26) and polycrystal silicon (24) layers; spacers (30') of silicon carbide are formed which cover the uncovered ends of the tungsten layer (26); and the sacrificial layer (21) is then removed.

Abstract translation: 为了提高形成的地震质量的悬挂结构（40）具有钨芯（26），所述传感器具有高密度的敏感性。 为了制造它，氧化硅的牺牲层（21），一多晶硅层（24），钨层（26）和碳化硅层（28）被连续超过单晶硅体沉积（1）; 悬浮结构（40）通过选择性地去除碳化硅（28），钨（26）和多晶硅（24）的层所定义; 覆盖钨层（26）的未覆盖端碳化硅的间隔件（30“）被形成; 和牺牲层（21）随后被移除。