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    Method of forming stacked wiring
    24.
    发明授权
    Method of forming stacked wiring 有权
    堆叠布线方法

    公开(公告)号：US09566790B2

    公开(公告)日：2017-02-14

    申请号：US14627393

    申请日：2015-02-20

    Applicant: Seiko Epson Corporation

    Inventor： Yoshihiko Yokoyama

    IPC: H05K3/06 ,  B41J2/16 ,  H05K3/46 ,  H05K3/38 ,  B41J2/14

    CPC classification number: B41J2/1629 ,  B41J2/14233 ,  B41J2/1433 ,  B41J2/1607 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/1643 ,  B41J2002/14491 ,  H05K3/06 ,  H05K3/061 ,  H05K3/062 ,  H05K3/064 ,  H05K3/383 ,  H05K3/384 ,  H05K3/467 ,  H05K2201/0364 ,  Y10T29/49401

    Abstract: A method of forming a stacked wiring includes forming a first adhesion layer on a substrate, forming a first wiring on the first adhesion layer, etching the first adhesion layer and the first wiring by the same first wet etching so that the first wiring is in a reverse trapezoid shape in which a first width of a top surface is larger than a second width of a bottom surface contacting the first adhesion layer as a cross-section in a direction intersecting with a first wiring extending direction, covering the top surface and a side surface of the first wiring with a second adhesion layer, forming a second wiring on the second adhesion layer, and etching the second adhesion layer and the second wiring by the same second wet etching so that the second adhesion layer and the second wiring remain on only the top surface of the first wiring.

    Abstract translation: 形成层叠布线的方法包括在基板上形成第一粘附层，在第一粘合层上形成第一布线，通过相同的第一湿蚀刻蚀刻第一粘合层和第一布线，使得第一布线处于 反向梯形，其中顶表面的第一宽度大于与第一粘合层接触的底面的第二宽度作为与第一布线延伸方向相交的方向的横截面，覆盖顶表面和侧面 所述第一布线的表面具有第二粘附层，在所述第二粘合层上形成第二布线，并且通过相同的第二湿蚀刻蚀刻所述第二粘合层和所述第二布线，使得所述第二粘合层和所述第二布线仅保留 第一个接线的顶面。

    SEMICONDUCTOR DEVICE
    26.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：EP2908338A1

    公开(公告)日：2015-08-19

    申请号：EP13846815.2

    申请日：2013-09-27

    Applicant: Fuji Electric Co., Ltd.

    Inventor： NAKAMURA, Hideyo ,  HORIO, Masafumi

    IPC: H01L25/07 ,  H01L25/18

    CPC classification number: H05K1/181 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/49833 ,  H01L24/17 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0212 ,  H05K1/0243 ,  H05K1/0296 ,  H05K3/3447 ,  H05K7/2089 ,  H05K2201/0364 ,  H05K2201/06 ,  H05K2201/09972 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    Abstract: Provided is a semiconductor device such that, while being small, it is possible to achieve low inductance responding to high speed switching. The semiconductor device includes a plurality of conductive pattern members (14), on each of which is mounted one or a plurality of power semiconductor chips (12A, 12B), and a printed circuit board (16) wherein a chip rod-form conductive connection member (17) connected to the power semiconductor chip and a pattern rod-form conductive connection member (17a, 17b) connected to the conductive pattern member are disposed on the surface opposing the conductive pattern member, wherein the conductive pattern member (14) is formed of a narrow portion (14b) and a wide portion (14a), the narrow portion of at least one conductive pattern member and the printed circuit board are connected by the pattern rod-form conductive connection member (17b), and a current path is formed between the conductive pattern member and the power semiconductor chip connected via the chip rod-form conductive connection member to the printed circuit board.

    Abstract translation: 提供一种半导体器件，其尽管很小，但可以实现响应于高速开关的低电感。 该半导体器件包括多个导电图案部件（14），其中每个导电图案部件安装有一个或多个功率半导体芯片（12A，12B）和印刷电路板（16），其中芯片棒状导电连接 与所述功率半导体芯片连接的部件（17）和与所述导电图案部件连接的图案棒状导电连接部件（17a，17b）设置在与所述导电图案部件相对的表面上，其中，所述导电图案部件（14） 由狭窄部分（14b）和宽部分（14a）形成，至少一个导电图案部件的窄部分和印刷电路板通过图案杆状导电连接部件（17b）连接，电流路径 形成在导电图案部件和经由芯片棒状导电连接部件连接到印刷电路板的功率半导体芯片之间。

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