公开(公告)号：US07180397B1

公开(公告)日：2007-02-20

申请号：US10783073

申请日：2004-02-20

Applicant: Galliano R. Busletta ,  Robert J. Roessler

Inventor： Galliano R. Busletta ,  Robert J. Roessler

IPC: H01F5/00

CPC classification number: H05K1/165 ,  H01F2027/2819 ,  H05K3/429 ,  H05K2201/086 ,  H05K2201/09063 ,  H05K2201/092 ,  H05K2201/09645

Abstract: The present invention provides a PWB for attaching electrical components thereto. The PWB includes a stack of insulating layers, conductive layers located between the insulating layers, wherein the conductive layers terminate at an edge of the PWB, and an edge plate interconnect located on the edge. The edge plate interconnect is free of a complementary via and contacts and electrically interconnects the conductive layers. The present invention also provides a method of making the PWB and also provides a power converter implementing the edge plate interconnects.

公开(公告)号：US20050189640A1

公开(公告)日：2005-09-01

申请号：US11055578

申请日：2005-02-09

Applicant: Kevin Grundy ,  Joseph Fjelstad ,  Gary Yasumura ,  William Wiedemann ,  Para Segaram

Inventor： Kevin Grundy ,  Joseph Fjelstad ,  Gary Yasumura ,  William Wiedemann ,  Para Segaram

IPC: H01L23/02 ,  H01L23/13 ,  H01L23/31 ,  H01L25/10 ,  H05K1/18 ,  H05K3/40

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/1059 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.

Abstract translation: 由多个封装，印刷电路板，连接器和插入件采用的结构，以产生减少与使用通孔相关联的有害信号质量问题的信号路径。 公开的结构可以与通孔实现共存。

公开(公告)号：US06178093B1

公开(公告)日：2001-01-23

申请号：US09033617

申请日：1998-03-03

Applicant: Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

Inventor： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

IPC: H05K111

CPC classification number: H05K3/4652 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/12044 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/025 ,  H05K3/246 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/092 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942 ,  Y10T428/249996 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at least one dielectric interior layer, wherein said first dielectric photoresist layer also includes at least one hole therein, said filler material also substantially filling said at least one hole within said first dielectric photoresist layer; a second wiring layer positioned on said first dielectric photoresist layer; wherein said second wiring layer includes a plurality of conductive pads as part thereof; and at least one external component electrically coupled to said conductive pads of said second wiring layer.

Abstract translation: 提供了一种信息处理系统，包括：金属外壳; 位于所述金属外壳内的至少一个电路组件，所述电路组件包括具有至少一个电介质内层的电路化基板，其包括第一表面和至少一个孔; 用于向所述金属外壳内的所述电路化基板提供电力的装置; 填充材料，其中所述填充材料基本上填充所述至少一个电介质内层中的所述至少一个孔; 位于所述至少一个电介质内层的所述第一表面上的第一布线层，其中所述第一布线层基本上覆盖其中具有所述填充材料的所述至少一个孔，所述第一布线层有助于将所述填充材料保持在所述至少一个 在所述至少一个电介质内层中的一个孔; 位于所述第一布线层和所述至少一个电介质内层的所述第一表面上的第一电介质光致抗蚀剂层，其中所述第一电介质光致抗蚀剂层还包括至少一个孔，所述填充材料还基本上填充所述至少一个孔 在所述第一电介质光致抗蚀剂层内; 位于所述第一电介质光致抗蚀剂层上的第二布线层; 其中所述第二布线层包括作为其一部分的多个导电焊盘; 以及电耦合到所述第二布线层的所述导电焊盘的至少一个外部部件。

公开(公告)号：US5387493A

公开(公告)日：1995-02-07

申请号：US599428

申请日：1990-10-18

Applicant: Shinichiro Imabayashi ,  Hitoshi Oka ,  Isamu Tanaka ,  Hiroshi Kikuchi ,  Makio Watanabe

Inventor： Shinichiro Imabayashi ,  Hitoshi Oka ,  Isamu Tanaka ,  Hiroshi Kikuchi ,  Makio Watanabe

IPC: G03F7/027 ,  G03F7/004 ,  G03F7/028 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18 ,  H05K3/42 ,  H05K3/46 ,  G03C1/492

CPC classification number: H05K3/185 ,  G03F7/004 ,  G03F7/028 ,  H05K3/4661 ,  H05K2201/0145 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K3/0023 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602

Abstract: A resin composition for forming conductor patterns comprising a photo curable resin, a photopolymerization initiator, a thermosetting resin, agent for the thermosetting resin, photosensitive semiconductor particles, and if necessary a polyfunctional unsaturated compound is suitable for forming very fine conductor patterns in a build-up method.

Abstract translation: 用于形成导体图案的树脂组合物，其包含光固化树脂，光聚合引发剂，热固性树脂，热固性树脂的试剂，光敏半导体颗粒，并且如果需要，多官能不饱和化合物适合于在构型中形成非常细的导体图案， up方法。

公开(公告)号：US4187339A

公开(公告)日：1980-02-05

申请号：US938104

申请日：1978-08-30

Applicant: Pierre-Henri Cayrol

Inventor： Pierre-Henri Cayrol

IPC: H01R12/51 ,  H05K1/09 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00 ,  B32B5/16

CPC classification number: H05K3/4664 ,  H05K1/095 ,  H05K2201/092 ,  H05K3/42 ,  H05K3/4602 ,  Y10S428/901 ,  Y10T29/49142 ,  Y10T29/49155 ,  Y10T428/24802 ,  Y10T428/24876 ,  Y10T428/24893 ,  Y10T428/24909 ,  Y10T428/24917

Abstract: A printed circuit has additional connections formed on one of its faces by depositing beads of conductive resin on that face. The conductive beads are covered by an insulating coating, and, if required, further conductive beads may be deposited on the insulating coating formed on the first beads.

Abstract translation: 印刷电路通过在该表面上沉积导电树脂珠而在其一个表面上形成附加连接。 导电珠被绝缘涂层覆盖，如果需要，可以在形成在第一珠上的绝缘涂层上沉积另外的导电珠。

公开(公告)号：EP1146780A2

公开(公告)日：2001-10-17

申请号：EP01302775.0

申请日：2001-03-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Muramatsu, Shigetsugu, Shinko Elec. Ind. Co., Ltd. ,  Imai, Kazunari, Shinko Elec. Ind. Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/3447 ,  H05K3/002 ,  H05K3/0032 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/092 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/1394 ,  Y10T29/49139

Abstract: A substrate (1,2,3) for mounting an electronic component (6) or components thereon. The substrate comprises a core substrate (20) and at least one insulation layer (22,22') on at least one side of the core substrate, and a patterned wiring line layer (24,24') formed on at least one insulation layer. The core substrate (20) includes holes (26a) in each of which a lead pin (6a) of an electronic component (6) may be inserted, and is provided with lands (10) each of which surround the opening of a hole and to which the lead pin (6a) inserted in the hole is bonded. The insulation layer (22,22') or layers has bores (11), which expose the land at their bottom ends, and thereby communicate with the holes. A method of manufacturing such a substrate is also disclosed.

公开(公告)号：EP0645953B1

公开(公告)日：1997-08-06

申请号：EP94114453.7

申请日：1994-09-14

Applicant: Siemens NV ,  MELEXIS ,  INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW

Inventor： van Puymbroeck, Josef ,  Bulcke, Fred ,  Beyne, Eric, Dr.

IPC: H05K3/46 ,  H01L23/02

CPC classification number: H05K1/183 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/49855 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/027 ,  H05K3/062 ,  H05K3/284 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09118 ,  H05K2201/092 ,  H05K2203/1581 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

公开(公告)号：EP0428870B1

公开(公告)日：1997-07-30

申请号：EP90119995.0

申请日：1990-10-18

Applicant: HITACHI, LTD.

Inventor： Imabayashi, Shinichiro ,  Oka, Hitoshi ,  Tanaka, Isamu ,  Kikuchi, Hiroshi ,  Watanabe, Makio

IPC: G03F7/038 ,  H05K3/46 ,  H05K3/18 ,  G03F7/004

CPC classification number: H05K3/185 ,  G03F7/004 ,  G03F7/028 ,  H05K3/0023 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0145 ,  H05K2201/092 ,  H05K2201/09845

公开(公告)号：EP2244291A1

公开(公告)日：2010-10-27

申请号：EP09158292.4

申请日：2009-04-20

Applicant: NXP B.V.

Inventor： Pischler, Erich

IPC: H01L23/485 ,  H01L23/498

CPC classification number: H01L24/10 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2223/6622 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/13 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/16106 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81898 ,  H01L2224/83136 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01R23/26 ,  H01R24/40 ,  H01R2103/00 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/184 ,  H05K2201/09036 ,  H05K2201/092 ,  H05K2201/09809 ,  H05K2201/09845 ,  Y10T29/49117 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A male connection component (120) for connection with a correspondingly configured female connection component (140) having a recess (144) extending into a main surface (170) of a female substrate (142) of the female connection component (140), wherein the female connection component (140) comprises a plurality of electrically conductive female contacts (146) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (170) of the female substrate (142), the male connection component (120) comprising a male substrate (102), a protrusion (104) protruding from a main surface (160) of the male substrate (102) and comprising a plurality of electrically conductive male contacts (106) which are electrically decoupled from one another and are arranged at different height levels with regard to the main surface (160) of the male substrate (102), wherein the male connection component (120) is adapted for connection with the female connection component (140) so that upon connection, each of the plurality of electrically conductive male contacts (106) is brought in contact with one of the plurality of electrically conductive female contacts (146) for providing electric contactation at different height levels, wherein the male substrate (102) forms at least part of one of a chip, a chip package and a circuit board.

Abstract translation: 用于与相应配置的阴连接部件（140）连接的阳连接部件（120），其具有延伸到阴连接部件（140）的阴基板（142）的主表面（170）的凹部（144），其中 阴连接部件（140）包括多个导电阴触头（146），它们彼此电分离并相对于阴基板（142）的主表面（170）布置在不同的高度水平处， 阳连接部件（120），包括阳基板（102），从阳基板（102）的主表面（160）突出并且包括多个导电阳触头（106）的突起（104） 并且相对于阳基板（102）的主表面（160）布置在不同的高度水平处，其中阳连接部件（120）适于与阴连接 连接部件（140），使得在连接时，多个导电阳触头（106）中的每一个与多个导电阴触头（146）中的一个接触，用于在不同的高度级别提供电接触，​​其中 阳基板（102）形成芯片，芯片封装和电路板之一的至少一部分。

公开(公告)号：EP1146780B1

公开(公告)日：2009-04-29

申请号：EP01302775.0

申请日：2001-03-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Muramatsu, Shigetsugu, c/o Shinko Electric Industries Co., Ltd. ,  Imai, Kazunari, c/o Shinko Electric Industries Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/3447 ,  H05K3/002 ,  H05K3/0032 ,  H05K3/0094 ,  H05K3/4602 ,  H05K2201/092 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/1394 ,  Y10T29/49139