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    Capacitor and method of manufacturing the same
    302.
    发明专利
    Capacitor and method of manufacturing the same 有权
    电容器及其制造方法

    公开(公告)号：JP2011023439A

    公开(公告)日：2011-02-03

    申请号：JP2009165280

    申请日：2009-07-14

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： HORIUCHI MICHIO ,  TOKUTAKE YASUE ,  MATSUDA YUICHI ,  SHIMIZU YUKIO ,  YAMAZAKI TOMOO ,  SAKAGUCHI YUTA

    IPC: H01G4/33 ,  H05K3/46

    CPC classification number: H05K1/162 ,  H01G4/012 ,  H01G4/232 ,  H01G4/302 ,  H05K1/0287 ,  H05K1/0306 ,  H05K2201/09263 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09945

    Abstract: PROBLEM TO BE SOLVED: To change the capacity easily without the design constraints, to accommodate increase in the capacity, and to facilitate incorporation of a capacitor in a substrate.
    SOLUTION: The capacitor 10 includes a dielectric substrate 11 and a large number of filamentous conductors 12 formed to penetrate through the dielectric substrate in the thickness direction thereof. An electrode 15a, 16a is connected to only respective one ends of a plurality of filamentous conductors 12 constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate 11, or in at least two positions on one of the surfaces. Further, an insulating layer 13, 14 is formed on each of both surfaces of the dielectric substrate 11 so as to cover regions between the electrodes 15a, 16a, and a conductor layer 15, 16 is formed on the corresponding insulating layer 13, 14 integrally with a desired number of electrodes 15a, 16a.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：容易地改变容量而没有设计限制，以适应容量的增加，并且有利于将电容器并入衬底中。 解决方案：电容器10包括电介质基板11和大量的在其厚度方向上穿过电介质基板的丝状导体12。 电极15a，16a仅连接在由多个丝状导体构成的组中的一组的多根丝状导体12的一端。 电极设置在电介质基板11的两个表面中的每一个上的至少一个位置，或者在其中一个表面上的至少两个位置。 此外，绝缘层13,14形成在电介质基板11的两个表面上，以覆盖电极15a，16a和导体层15之间的区域，16形成在相应的绝缘层13,14上。 具有所需数量的电极15a，16a。 版权所有（C）2011，JPO＆INPIT

    Printed wiring board
    303.
    发明专利
    Printed wiring board 审中-公开
    印刷线路板

    公开(公告)号：JP2009290124A

    公开(公告)日：2009-12-10

    申请号：JP2008143449

    申请日：2008-05-30

    Applicant: Fujitsu Ltd ,  富士通株式会社

    Inventor： YOSHIMURA HIDEAKI ,  IIDA KENJI ,  ABE TOMOYUKI ,  MAEHARA YASUTOMO ,  HIRANO SHIN

    IPC: H05K1/11 ,  H05K3/46

    CPC classification number: H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09809

    Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board capable of suppressing the generation of stress.
    SOLUTION: In the printed wiring board 11, the same structure is established which includes a large-diameter via 18, a filler 21 for a lower hole, and a through-hole 24 and a small-diameter via 25 in each of the through-holes 17 for lower holes distributed to at least a specific region. As a result, at a specific region, a ratio of the filler 21 for lower holes and that of a core layer 13 are prescribed to a uniform distribution in an in-plane direction of the core layer 13, thus suppressing the generation of a warp caused by the thermal stress in the in-plane direction of the core layer 13. Also, when all the through-holes 17 for lower holes distributed to at least a specific region are disposed mutually equally, the warp caused by the thermal stress in the in-plane direction of the core layer 13 is avoided reliably.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够抑制应力产生的印刷线路板。 解决方案：在印刷电路板11中，建立了相同的结构，其包括大直径通孔18，用于下孔的填料21，以及通孔24和小直径通孔25 用于下孔的通孔17分布到至少特定区域。 结果，在特定区域，下部孔用填料21和芯层13的填料21的比例规定为在芯层13的面内方向上的均匀分布，从而抑制翘曲的产生 由芯层13的面内方向的热应力引起的。另外，当分布在至少特定区域的所有用于下部孔的通孔17相互平等地布置时，由于在 可靠地避免芯层13的面内方向。 版权所有（C）2010，JPO＆INPIT

    Wiring substrate, manufacturing method thereof, and semiconductor package
    305.
    发明专利
    Wiring substrate, manufacturing method thereof, and semiconductor package 审中-公开
    接线基板，其制造方法和半导体封装

    公开(公告)号：JP2009194321A

    公开(公告)日：2009-08-27

    申请号：JP2008036234

    申请日：2008-02-18

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： KOBAYASHI KAZUKI

    IPC: H05K1/02 ,  H01L23/00 ,  H01L23/12 ,  H05K3/00

    CPC classification number: H05K1/0266 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/114 ,  H05K3/244 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09936 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a wiring substrate capable of forming substrate management information without increasing the manufacturing cost too much and enabling high-density packaging, to provide a manufacturing method thereof, and to provide a semiconductor package containing the wiring substrate. SOLUTION: A wiring substrate includes an alternate lamination of wiring layers and insulating layers wherein the adjacent wiring layers are electrically interconnected through via-holes formed on the insulating layer. The outermost one of the insulating layers has a plurality of holes forming substrate management information capable of being recognized as characters and symbols. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 解决问题：为了提供能够形成基板管理信息而不增加制造成本太多并能够进行高密度封装的布线基板，提供其制造方法，并且提供包含布线基板的半导体封装 。 解决方案：布线基板包括布线层和绝缘层的交替叠层，其中相邻布线层通过形成在绝缘层上的通孔电互连。 绝缘层中最外面的一个具有形成能被识别为字符和符号的衬底管理信息的多个孔。 版权所有（C）2009，JPO＆INPIT

    Multilayer wiring board
    307.
    发明专利
    Multilayer wiring board 有权
    多层接线板

    公开(公告)号：JP2008153542A

    公开(公告)日：2008-07-03

    申请号：JP2006341778

    申请日：2006-12-19

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： HIRAKAWA HIDEKAZU

    IPC: H05K3/46

    CPC classification number: H05K1/0219 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/10674

    Abstract: PROBLEM TO BE SOLVED: To prevent a deterioration in electrical characteristics of a multilayer circuit board on which signal, ground and power supply lines are densely arranged even when its density is increased.
    SOLUTION: The multilayer wiring board has a structure in which first wiring layers 12A to 12D having one or several kinds of lines out of the signal line 25 having signal electrodes 15, the power supply line 26 having power supply electrodes 16 or the ground line 27 having ground electrodes 17 and several first insulating layers 11A to third insulating layers 11C which are alternately stacked. In this case, the signal line 25 and the power supply line 26 or the signal line 25 and the ground line 27 are alternately arranged on the first wiring layer 12A of the insulating layer.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：为了防止信号，接地和电源线在其密度增加时密集布置的多层电路板的电特性的劣化。 解决方案：多层布线板具有这样的结构，其中具有信号线25的信号线25中具有一条或几条线的第一布线层12A至12D，具有电源电极16的电源线26或 地线27具有接地电极17和交替堆叠的多个第一绝缘层11A至第三绝缘层11C。 在这种情况下，信号线25和电源线26或信号线25和接地线27交替布置在绝缘层的第一布线层12A上。 版权所有（C）2008，JPO＆INPIT

    Method of manufacturing wiring board
    309.
    发明专利
    Method of manufacturing wiring board 审中-公开
    制造接线板的方法

    公开(公告)号：JP2005026313A

    公开(公告)日：2005-01-27

    申请号：JP2003187669

    申请日：2003-06-30

    Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

    Inventor： HORIKAWA YASUYOSHI ,  MUTSUKAWA AKIO ,  IIJIMA TAKAHIRO

    IPC: H05K3/40 ,  H01L21/48 ,  H05K3/44 ,  H05K3/46

    CPC classification number: H01L21/486 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K3/445 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2203/025 ,  H01L2224/0401

    Abstract: PROBLEM TO BE SOLVED: To provide a method of flattening a level difference caused by the projection of a conductive part without any trouble, in a manufacturing method of a wiring board which has a structure wherein the conductive part is inserted into the through-hole of a core board while having the projection protruding from the core board. SOLUTION: The method of flattening a level difference comprises processes of preparing the core board 10 equipped with a through-hole 10a arranging the conductive part 20 in the through-hole 10a making the tips of the conductive part 20 serve as projections 20a and 20b protruding from the core board 10 by inserting the conductive part 20 longer than the thickness of the core board 10 into the through-hole 10a of the core board 10, forming insulating films 12a and 12b on the core board 10 so as to cover the projections 20a and 20b of the conductive part 20, and flattening the insulating films 12a and 12b by grinding them. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供一种在没有任何问题的情况下平坦化由导电部件的突出引起的电平差的方法，在布线板的制造方法中，其具有将导电部插入到通孔 同时具有从芯板突出的突出部的芯板的孔。 解决方案：平坦化水平差的方法包括制备具有将导电部分20布置在通孔10a中的通孔10a的芯板10的工艺，使得导电部分20的末端用作突起20a 并且通过将比芯芯10的厚度长的导电部20插入到芯板10的通孔10a中，从芯板10突出，并且在芯板10上形成绝缘膜12a和12b以覆盖 导电部20的突出部20a，20b，通过研磨绝缘膜12a，12b使其平坦化。 版权所有（C）2005，JPO＆NCIPI

    Conductive sheet
    310.
    发明专利
    Conductive sheet 审中-公开
    导电片

    公开(公告)号：JP2005019513A

    公开(公告)日：2005-01-20

    申请号：JP2003179343

    申请日：2003-06-24

    Applicant: Fcm Kk ,  Fcm株式会社

    Inventor： MIURA SHIGENORI

    IPC: H05K1/11 ,  H05K1/00 ,  H05K3/42

    CPC classification number: H05K1/0287 ,  H05K1/0393 ,  H05K3/426 ,  H05K2201/09609

    Abstract: PROBLEM TO BE SOLVED: To provide a conductive sheet which has reliable electric connectivity, reduced in production cost, and improved in dimensional accuracy simultaneously.
    SOLUTION: A conductive layer is formed on both the front and rear surface of the insulating base of the conductive sheet respectively, the conductive layers formed on the surfaces of the insulating base are electrically connected together through a through-hole bored in the insulating base penetrating through it, and the conductive layer of the same composition is formed on the front and rear surface of the insulating base and on the inner wall of the through-hole in the same process.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有可靠的电连接性，降低生产成本并且同时提高尺寸精度的导电片。 解决方案：在导电片的绝缘基底的前表面和后表面上分别形成导电层，形成在绝缘基底表面上的导电层通过钻孔的通孔电连接在一起 绝缘基底穿透它，并且在相同工艺中，绝缘基底的前后表面和通孔的内壁上形成相同组成的导电层。 版权所有（C）2005，JPO＆NCIPI

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