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    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE
    31.
    发明公开
    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE 审中-公开

    公开(公告)号：US20240074191A1

    公开(公告)日：2024-02-29

    申请号：US18175907

    申请日：2023-02-28

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong ZHU

    IPC: H10B43/27 ,  H10B51/20

    CPC classification number: H10B43/27 ,  H10B51/20

    Abstract: A memory device, a method of manufacturing the same, and an electronic apparatus including the same. The memory device includes: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source/drain region and an upper source/drain region located at different vertical heights and a channel region between the lower source/drain region and the upper source/drain region; a gate stack on the substrate and extending vertically relative to the substrate to pass through the cell active layers, the gate stack including a gate conductor layer and a memory functional layer arranged between the gate conductor layer and the cell active layers, and a memory cell being defined at an intersection of the gate stack and each cell active layer; and a conductive metal layer arranged on a lower surface of each cell active layer and/or an upper surface of each cell active layer.

    Memory device and method for manufacturing the same, and electronic apparatus including the memory device
    32.
    发明授权
    Memory device and method for manufacturing the same, and electronic apparatus including the memory device 有权

    公开(公告)号：US11895845B2

    公开(公告)日：2024-02-06

    申请号：US17309222

    申请日：2018-12-13

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huilong Zhu

    IPC: H10B51/20 ,  H01L21/28 ,  H10B43/27

    CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/40117 ,  H10B43/27

    Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure. A first effective work function of a combination of the first electrode layer and the first gate dielectric layer is different from a second effective work function of a combination of the second electrode layer and the second gate dielectric layer.

    MEMORY DEVICE, METHOD OF MANUFACTURING MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE
    36.
    发明公开
    MEMORY DEVICE, METHOD OF MANUFACTURING MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE 审中-公开

    公开(公告)号：US20230380132A1

    公开(公告)日：2023-11-23

    申请号：US18311528

    申请日：2023-05-03

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong ZHU

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction, and adjacent connection line layers respectively include conductive lines extending in directions intersected; a plurality of memory cells respectively including first and second transistors stacked. A first active layer of the first transistor includes first and second source/drain regions respectively electrically connected with conductive lines in the first and second connection line layers. A second active layer of the second transistor includes a first source/drain region electrically connected with a gate conductor layer of the first transistor, and a second source/drain region electrically connected with a conductive line in the third connection line layer. A gate conductor layer of the second transistor of each memory cell is electrically connected to a conductive line in the fourth connection line layer.

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