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公开(公告)号：KR1020140003955A
公开(公告)日：2014-01-10
申请号：KR1020120071875
申请日：2012-07-02
Applicant: 삼성전기주식회사
CPC classification number: H05K1/182 , H05K1/0231 , H05K1/185
Abstract: The present invention relates to a capacitor embedded board. The capacitor embedded board according to the present invention includes: first to fourth layers which form a stacked structure of four layers; and at least one capacitor which is embedded in the second layer and the third layer among the first to fourth layers. Capacitors embedded in the second layer and the third layer are respectively and electrically connected to at least one among power terminals and grounding terminals of active devices and form a mutually parallel connection structure of the capacitors by unifying the wires of the power terminal in the second layer or the third layer. By the present invention, the capacitors are embedded in a base board of the stacked structure with multiple layers. The capacitor embedded board is formed to reduce impedance in a whole frequency area and has high capacitance and low equivalent inductance by efficiently connecting the capacitors embedded in the base board in parallel.
Abstract translation: 本发明涉及一种电容器嵌入式板。 根据本发明的电容器嵌入板包括：形成四层的叠层结构的第一至第四层; 以及嵌入第一层和第三层中的第二层和第三层中的至少一个电容器。 嵌入在第二层和第三层中的电容器分别电连接到有源器件的电源端子和接地端子中的至少一个，并且通过将第二层中的电源端子的电线统一起来形成电容器的相互平行的连接结构 或第三层。 通过本发明，将电容器嵌入具有多层的层叠结构的基板。 电容器嵌入板形成为通过有效地将嵌入基板中的电容器并联连接来降低整个频率区域的阻抗并具有高电容和低等效电感。
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公开(公告)号：KR101072591B1
公开(公告)日：2011-10-11
申请号：KR1020090073444
申请日：2009-08-10
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0236 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H05K2201/09309 , H05K2201/09627 , H01L2924/00014
Abstract: EMI 노이즈저감인쇄회로기판이개시된다. 상기인쇄회로기판은, 대역저지주파수특성을갖는전자기밴드갭구조가내부에삽입되는다층인쇄회로기판으로서, 그라운드층과전원층이마련되는제1 영역과; 상기제1 영역의측면에위치하여, 상기제1 영역의측면을통해외부로방사되는 EMI 노이즈를차폐하도록상기전자기밴드갭구조가마련되는제2 영역을포함하되, 상기전자기밴드갭구조는, 상기인쇄회로기판의가장자리를따라위치하는복수개의제1 도전판과; 상기제1 도전판과다른평면상에, 상기제1 도전판과교번하도록배치되는복수개의제2 도전판과; 상기제1 도전판과상기제2 도전판을연결하는비아를포함한다.
Abstract translation: 作为多层板，具有插入板的内部的具有带阻频率特性的电磁带隙结构的EMI降噪板包括形成有接地层和功率层的第一区域，以及 第二区域，放置在第一区域的侧表面上，其中形成有电磁带隙结构，以便屏蔽通过第一区域的侧表面辐射到外部的EMI噪声。 电磁带隙结构包括沿板的边缘放置的多个第一导电板，多个第二导电板，设置在不同于第一导电板的平面上，使得第二导电板交替地布置有 第一导电板和将第一导电板连接到第二导电板的通孔。
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公开(公告)号：KR100956689B1
公开(公告)日：2010-05-10
申请号：KR1020080062000
申请日：2008-06-27
Applicant: 삼성전기주식회사
CPC classification number: H01P1/20345 , H01P1/2005 , H05K1/0236 , H05K3/429 , H05K2201/09309 , H05K2201/09518 , H05K2201/09627 , H05K2201/09681
Abstract: 전자기 밴드갭 구조물 및 이를 포함하는 인쇄회로기판이 개시된다. 본 발명의 실시예에 따르면 2개의 도전층 사이에 위치하는 복수개의 도전판과, 상기 도전판들 중 어느 2개의 도전판 간을 각각 전기적으로 연결하는 스티칭 비아를 포함하는 전자기 밴드갭 구조물에 있어서, 상기 스티칭 비아는, 일단이 상기 2개의 도전판 중 어느 하나와 연결되는 제1 비아; 일단이 상기 2개의 도전판 중 다른 하나와 연결되는 제2 비아; 상기 2개의 도전층 사이에서 상기 도전판들과 다른 평면 상에 위치하여, 상기 제1 비아의 타단과 상기 제2 비아의 타단 간을 전기적으로 연결하는 연결 패턴을 포함하되, 상기 제1 비아 및 상기 제2 비아 중 어느 하나는 상기 2개의 도전층 중 적어도 어느 하나와 동일한 평면 상을 관통하도록 형성되는 것을 특징으로 하는 전자기 밴드갭 구조물이 제공된다.
인쇄회로기판, 전자기 밴드갭 구조물, 스티칭 비아, PTHAbstract translation: 公开了一种电磁带隙结构和包括该电磁带隙结构的印刷电路板。 根据本发明的实施例，提供了一种电磁带隙结构，其包括位于两个导电层之间的多个导电板以及电连接导电板中的任意两个导电板的拼接通孔， 其中，拼接通孔包括：第一通孔，其一端连接至两个导电板中的一个; 第二通孔，其一端连接到两个导电板中的另一个; 并且连接图案位于与两个导电层之间的导电板不同的平面上，并且电连接第一通孔的另一端和第二通孔的另一端， 并且形成第二通孔中的一个以便穿过与两个导电层中的至少一个导电层相同的平面。
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公开(公告)号：KR1020100001910A
公开(公告)日：2010-01-06
申请号：KR1020080062000
申请日：2008-06-27
Applicant: 삼성전기주식회사
CPC classification number: H01P1/20345 , H01P1/2005 , H05K1/0236 , H05K3/429 , H05K2201/09309 , H05K2201/09518 , H05K2201/09627 , H05K2201/09681
Abstract: PURPOSE: An electromagnetic band gap structure and a printed circuit board are provided to simplify a total process by reducing the number of laminating processes when an electromagnetic band gap structure is applied to a multilayer printed circuit board structure. CONSTITUTION: A plurality of conductive plates is arranged between two conductive layers. A stitching via(745) electrically connects the two conductive plates, and includes a first via(741), a second via(732), and a connecting pattern(743). One end of the first via is connected to one among the two conductive plates. One end of the second via is connected to one among the two conductive plates. The connecting pattern electrically connects the other end of the first via to the other end of the second via.
Abstract translation: 目的：提供电磁带隙结构和印刷电路板，以便在将电磁带隙结构应用于多层印刷电路板结构时，通过减少层压处理次数来简化总体处理。 构成：在两个导电层之间布置多个导电板。 缝合通孔（745）电连接两个导电板，并且包括第一通孔（741），第二通孔（732）和连接图案（743）。 第一通孔的一端连接到两个导电板中的一个。 第二通孔的一端连接到两个导电板中的一个。 连接图案将第一通孔的另一端电连接到第二通孔的另一端。
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公开(公告)号：KR1020090060117A
公开(公告)日：2009-06-11
申请号：KR1020080057443
申请日：2008-06-18
Applicant: 삼성전기주식회사
CPC classification number: H01P1/2005 , H01L2224/16225
Abstract: An electromagnetic band gap structure and a printed circuit board are provided to remove a limit about design and arrangement by securing high inductance and impedance. An electromagnetic band gap structure(300) includes a dielectric layer(320), a plurality of conductive plates, and a stitching via(340). The stitching via electrically connects two conductive plates. The stitching via includes a first via(341), a second via(342), a connection pattern(343), and a first extension pattern(344). The first via and the second via penetrates the dielectric layer. One end of the first via is positioned in the same plane as one among two conductive plates. One end of the second via is positioned in the same plane as the other one among two conductive plates. One end of the connection pattern is connected to the other end of the first via. The other end of the connection pattern is connected to the other end of the second via. One end of the first extension pattern is connected to one end of the first via. The other end of the first extension pattern is connected to one conductive plate.
Abstract translation: 提供电磁带隙结构和印刷电路板，通过确保高电感和阻抗来消除设计和布置的限制。 电磁带隙结构（300）包括电介质层（320），多个导电板和缝合通孔（340）。 缝合通过电连接两个导电板。 缝合通孔包括第一通孔（341），第二通孔（342），连接图案（343）和第一延伸图案（344）。 第一通孔和第二通孔穿透介电层。 第一通孔的一端位于与两个导电板中的一个相同的平面中。 第二通孔的一端位于与两个导电板中的另一个相同的平面中。 连接图案的一端连接到第一通孔的另一端。 连接图案的另一端连接到第二通孔的另一端。 第一延伸图案的一端连接到第一通孔的一端。 第一延伸图案的另一端连接到一个导电板。
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Patent Agency Ranking
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公开(公告)号：KR1020180055621A
公开(公告)日：2018-05-25
申请号：KR1020160164516
申请日：2016-12-05
Applicant: 삼성전기주식회사
IPC: H01L25/065 , H01L25/07 , H01L25/11 , H01L23/538 , H01L23/498 , H01L23/525 , H01L23/31
CPC classification number: H01L2224/18 , H01L2224/32145 , H01L2224/48091 , H01L2924/00014 , H01L25/0657 , H01L23/3114 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5226 , H01L23/525 , H01L23/5383 , H01L23/5384 , H01L25/073 , H01L25/117
Abstract: 본개시는관통홀을갖는제1연결부재, 상기관통홀에배치된제1 및제2반도체칩, 상기제1연결부재와상기제1 및제2반도체칩의적어도일부를봉합하는봉합재, 및상기제1연결부재와상기제1 및제2반도체칩의활성면상에배치된제2연결부재를포함하며, 상기제2연결부재의재배선층은제1도체및 제2도체를통해상기제1접속패드및 상기제2접속패드와각각연결되되, 상기제2도체가상기제1도체보다높이가큰, 팬-아웃반도체패키지에관한것이다.
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公开(公告)号：KR1020170041048A
公开(公告)日：2017-04-14
申请号：KR1020150140502
申请日：2015-10-06
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0253 , H01P3/08 , H01P3/081 , H01P3/085 , H05K1/0225 , H05K1/0298 , H05K2201/09263 , H05K2201/09681 , H05K2201/09781
Abstract: 본개시는절연층을사이에두고제1 및제2 도체층이배치되며, 상기제1 및제2 도체층은각각신호라인과접지라인을포함하며, 상기신호라인과상기접지라인의대응영역에있어서, 상기신호라인에대응되는상기접지라인의패턴형상이상기신호라인의위치별임피던스차이가최소가되도록패턴화된회로기판및 상기회로기판의접지라인으로이용할수 있는도체패턴구조에관한것이다.
Abstract translation: 本发明的特征在于，第一导体层和第二导体层隔着绝缘层配置，第一导体层和第二导体层分别具有信号线和接地线，在信号线和接地线的对应区域中， 本发明涉及一种导体图案结构，其可以用作电路板的图案化电路板和接地线，使得对应于信号线的接地线的每个图案线的阻抗差异最小化。
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公开(公告)号：KR1020140087744A
公开(公告)日：2014-07-09
申请号：KR1020120158339
申请日：2012-12-31
Applicant: 삼성전기주식회사
CPC classification number: H05K1/185 , H01L2224/16227 , H01L2924/15313 , H05K1/0231 , H05K3/4602 , H05K3/4644 , H05K2201/10015 , Y10T29/49139
Abstract: The present invention relates to an electronic component-embedded substrate. The electronic component-embedded substrate comprises: a first insulating layer which includes a cavity and is provided with a first circuit pattern and a second circuit pattern on upper and lower surfaces thereof; an electronic component, at least a portion of which is inserted into the cavity, and which includes an external electrode; a plurality of build-up insulating layers which are laminated on upper and lower sides thereof; an upper circuit pattern and a lower circuit pattern which are formed on the build-up insulating layers; a plurality of vias which connect the external electrode, the upper circuit pattern, the first circuit pattern, the second circuit pattern, and the lower circuit pattern to form an electric loop. Therefore, an impedance of a path through the electronic component and an external device is connected can be reduced, compared to the prior art.
Abstract translation: 本发明涉及电子元件嵌入式基板。 电子部件嵌入式基板包括：第一绝缘层，其包括空腔，并且在其上表面和下表面上设置有第一电路图案和第二电路图案; 电子部件，其至少一部分插入到所述空腔中，并且包括外部电极; 叠层在其上侧和下侧的多个堆积绝缘层; 形成在积层绝缘层上的上电路图案和下电路图案; 连接外部电极，上部电路图案，第一电路图案，第二电路图案和下部电路图案的多个通孔，形成电气回路。 因此，与现有技术相比，可以减少通过电子部件和外部装置的路径的阻抗。
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公开(公告)号：KR101044789B1
公开(公告)日：2011-06-29
申请号：KR1020100000088
申请日：2010-01-04
Applicant: 삼성전기주식회사
CPC classification number: H05K1/0236 , H05K1/165 , H05K2201/09309 , H05K2201/09627 , H05K2201/097
Abstract: PURPOSE: An electromagnetic band gap structure and circuit board are provided to arrange an electromagnetic band gap structure with a specific structure in a circuit board, thereby reducing conductive noise. CONSTITUTION: An electromagnetic band gap structure includes a plurality of conductive plates and a stitching via unit. The stitching via unit electrically connects two conductive plates. One end of a first via is connected to one of the two conductive plates. One end of the second via is connected to the other one of the two conductive plates. A spiral connection unit has a spiral serial connection structure. A first conductive connection pattern connects one end of the spiral connection unit with the other end of the first via. A second connection pattern connects the other end of the spiral connection unit with the other end of the second via.
Abstract translation: 目的：提供电磁带隙结构和电路板，以在电路板中布置具有特定结构的电磁带隙结构，从而降低导电噪声。 构成：电磁带隙结构包括多个导电板和缝合通孔单元。 缝合通孔单元电连接两个导电板。 第一通孔的一端连接到两个导电板中的一个。 第二通孔的一端连接到两个导电板中的另一个。 螺旋连接单元具有螺旋串联连接结构。 第一导电连接图案将螺旋连接单元的一端与第一通孔的另一端连接。 第二连接图案将螺旋连接单元的另一端与第二通孔的另一端连接。
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