公开(公告)号：KR1020040032352A

公开(公告)日：2004-04-17

申请号：KR1020020061453

申请日：2002-10-09

Applicant: 삼성전자주식회사

Inventor： 김광복 ,  고용선 ,  황인석 ,  김경현

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a metal line is provided to be capable of applying a damascene process and preventing an erosion phenomenon. CONSTITUTION: A structure(32) having a plurality of recess portions(32a) is formed on a substrate(30). A spacer layer(36) is formed at both sidewalls of each recess portion. A tungsten layer is formed on the entire surface of the resultant structure for completely filling the recess portions. At this time, the spacer layer has a polishing selectivity ratio larger than that of the tungsten layer as much as at least 50 times. A polishing process is performed on the tungsten layer until the upper surface of the structure is exposed. Preferably, at least two recess portions are formed on the structure and have different line widths. Preferably, the recess portion is contact hole or via hole. Preferably, the structure is made of an oxide layer.

Abstract translation: 目的：提供一种用于形成金属线的方法，以能够应用镶嵌工艺并防止侵蚀现象。 构成：在基板（30）上形成具有多个凹部（32a）的结构体（32）。 间隔层（36）形成在每个凹部的两个侧壁处。 在所得结构的整个表面上形成钨层，以完全填充凹部。 此时，间隔层的抛光选择率比钨层的抛光选择率多至少50倍。 在钨层上进行抛光处理，直到暴露结构的上表面。 优选地，在结构上形成至少两个凹部，并具有不同的线宽。 优选地，凹部是接触孔或通孔。 优选地，该结构由氧化物层制成。

公开(公告)号：KR1020030010212A

公开(公告)日：2003-02-05

申请号：KR1020010045070

申请日：2001-07-26

Applicant: 삼성전자주식회사

Inventor： 조민수 ,  김동준 ,  류의열 ,  김대근 ,  김용희 ,  하상록 ,  김광복 ,  남정림 ,  김경현

IPC: H01L21/3105

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/66553

Abstract: PURPOSE: A method for planarizing a non-volatile memory is provided to remove a stepper portion between a cell region of a flash memory device and a peripheral region of a logic device in a process for forming a word line. CONSTITUTION: A floating gate structure is formed on a cell region of a semiconductor substrate(100). A conductive layer(113) is formed on the floating gate structure and the semiconductor substrate(100). A hard mask layer is formed on the conductive layer(113). The first insulating layer is formed on the hard mask layer. The first insulating layer is removed from the cell region. The first insulating layer pattern is formed on a peripheral region. The hard mask layer is removed from the cell region. The second insulating layer(125) is formed on the first insulating layer pattern. The cell region and the peripheral region are planarized by removing the second insulating layer(125) and the first insulating layer pattern. A word line is formed on both sidewalls of the floating gate structure by patterning the conductive layer(113). A gate of a logic device is formed on the peripheral region.

Abstract translation: 目的：提供用于平坦化非易失性存储器的方法，以在形成字线的过程中去除闪速存储器件的单元区域与逻辑器件的外围区域之间的步进器部分。 构成：在半导体衬底（100）的单元区域上形成浮栅结构。 在浮栅结构和半导体衬底（100）上形成导电层（113）。 在导电层（113）上形成硬掩模层。 第一绝缘层形成在硬掩模层上。 第一绝缘层从电池区域移除。 第一绝缘层图案形成在周边区域上。 从单元区域去除硬掩模层。 第二绝缘层（125）形成在第一绝缘层图案上。 通过去除第二绝缘层（125）和第一绝缘层图案来平坦化单元区域和周边区域。 通过图案化导电层（113），在浮栅结构的两个侧壁上形成字线。 逻辑器件的栅极形成在周边区域上。

公开(公告)号：KR1020030006407A

公开(公告)日：2003-01-23

申请号：KR1020010042123

申请日：2001-07-12

Applicant: 삼성전자주식회사

Inventor： 송장근 ,  김경현 ,  유재진 ,  이승희 ,  박승범 ,  최용우

IPC: G02F1/1335

CPC classification number: G02F1/133707 ,  G02F1/134336 ,  G02F1/136213 ,  G02F1/1393 ,  G02F2201/121

Abstract: PURPOSE: A vertical alignment type liquid crystal display device and a color filter substrate used in the LCD are provided to reduce the color shift among gray levels by forming cell gap of blue color filter smaller than the other color filters, thereby realizing a high definition LCD. CONSTITUTION: A vertical alignment type liquid crystal display device includes a first insulating substrate(10), first wires formed on the first substrate, second wires(70) formed on the first substrate intersecting the first wires, pixel electrodes(91) formed in pixel areas defined by the intersection between the first and second wires and having a first opening pattern, thin film transistors connected to the first and second wires and the pixel electrodes, a second insulating substrate(100) facing the first substrate, red, green and blue color filters(310-330) formed on the second substrate, common electrodes(400) formed on the second substrate and having a second opening pattern, and a liquid crystal layer(900) implanted between the first and second substrates and having liquid crystal molecules aligned vertically with respect to the substrates when no electric fields are applied between the pixel and common electrodes, wherein cell gap B representing a thickness of the liquid crystal layer below the blue color filter area has different size from cell gaps R or G respectively representing thickness of the liquid crystal layer below the red or green color filter.

Abstract translation: 目的：提供LCD中使用的垂直取向型液晶显示装置和滤色器基板，通过使蓝色滤色片的单元间隙小于其他滤色片来减少灰度之间的色彩偏移，从而实现高清晰度LCD 。 构成：垂直取向型液晶显示装置包括第一绝缘基板（10），形成在第一基板上的第一布线，与第一布线交叉的第一基板上形成的第二布线（70），形成在像素 由第一和第二布线之间的交点限定并且具有第一开口图案的区域，连接到第一和第二布线和像素电极的薄膜晶体管，面对第一基板的第二绝缘基板（100），红色，绿色和蓝色 形成在第二基板上的滤色器（310-330），形成在第二基板上并具有第二开口图案的公共电极（400）和注入在第一和第二基板之间并具有液晶分子的液晶层（900） 在像素和公共电极之间没有施加电场时相对于基板垂直排列，其中单元间隙B表示液晶的厚度 蓝色滤色器区域以下的层分别具有与分别表示红色或绿色滤色器下方的液晶层的厚度的单元间隙R或G不同的尺寸。

公开(公告)号：KR1020020093222A

公开(公告)日：2002-12-16

申请号：KR1020010031676

申请日：2001-06-07

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  김경현 ,  이용탁

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L21/3212 ,  H01L23/544 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A method of forming a memory device having a capacitor including a high dielectric constant layer is provided to form a tungsten contact plug of good conductivity connected to a capacitor lower electrode without damaging an alignment key in a memory device using the high dielectric capacitor. CONSTITUTION: A contact hole and a groove for the alignment key are formed in a substrate. A conductive layer is formed to fill the contact hole and cover the inner sidewall of the groove. A capping layer for an oxygen barrier is conformally stacked on the conductive layer. A chemical mechanical polishing(CMP) process is performed to etch the capping layer and the conductive layer so that the contact plug filling the contact hole and the conductive layer and capping layer covering the inner sidewall of the groove are left. A capacitor lower electrode layer is stacked to come in contact with the upper surface of the contact plug. A high dielectric layer is formed on the lower electrode layer. A high temperature oxidation process is performed to crystallize the high dielectric layer.

Abstract translation: 目的：提供一种形成具有包括高介电常数层的电容器的存储器件的方法，以形成具有良好导电性的钨接触插塞，其连接到电容器下电极，而不会损坏使用高介电电容器的存储器件中的对准键。 构成：在基板中形成用于对准键的接触孔和凹槽。 形成导电层以填充接触孔并覆盖凹槽的内侧壁。 用于氧阻挡层的覆盖层共形堆叠在导电层上。 进行化学机械抛光（CMP）工艺以蚀刻覆盖层和导电层，使得填充接触孔的接触塞和覆盖槽的内侧壁的导电层和覆盖层留下。 电容器下电极层被层叠以与接触插塞的上表面接触。 在下电极层上形成高介电层。 进行高温氧化处理以使高介电层结晶。

公开(公告)号：KR100350643B1

公开(公告)日：2002-08-28

申请号：KR1019990047564

申请日：1999-10-29

Applicant: 삼성전자주식회사

Inventor： 류재진 ,  박승범 ,  김경현 ,  송장근

IPC: G02F1/1343

Abstract: 하부기판위에가로방향의게이트선과게이트선의분지인게이트전극및 게이트선과나란한유지전극선이형성되어있다. 게이트선, 게이트전극및 유지전극선은게이트절연막으로덮여있으며그 위에는반도체층과저항성접촉층이형성되어있다. 데이터선이세로방향으로형성되어있고, 데이터선에서이어진소스전극과소스전극맞은편의드레인전극이게이트전극상부에형성되어있다. 데이터선과소스및 드레인전극의상부에는보호절연막이형성되어있다. 게이트선과데이터선이교차하는영역에의해정의되는화소영역에는모서리가곡선화된사각형수 개가연결되어있는형태의화소전극이형성되어있으며화소전극의일부는드레인전극과접촉하고있다. 데이터선사이의게이트선상부에는게이트선과절연되어있는게이트선보조패턴이형성되어있다. 상부기판의공통전극에는중심으로부터멀어질수록폭이좁아지는모양의십자모양(+) 수개가일렬로배열되어있는개구패턴이형성되어있다. 이때, 화소전극을이루는사각형간의간격및 개구패턴의폭을상부기판과하부기판간의거리보다크게형성하여비정상조직의발생이줄어든다.

公开(公告)号：KR1020020052646A

公开(公告)日：2002-07-04

申请号：KR1020000082057

申请日：2000-12-26

Applicant: 삼성전자주식회사

Inventor： 한자형 ,  한명식 ,  김경현 ,  홍창기

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: PURPOSE: A method for fabricating a non-volatile memory device is provided to simplify a fabricating process, reduce thickness of interlayer dielectric, and improve a speed characteristic of a semiconductor device. CONSTITUTION: A gate pattern(120) is formed on a semiconductor substrate(100). A polishing stopper(114) is formed on the semiconductor substrate(100) including the gate pattern(120) by using a blanket method. A multi-layer including an interlayer dielectric(116) is deposited on the gate pattern(120). The interlayer dielectric(116), the polishing stopper(114), and a gate oxide layer of a common source line formation region are etched partially by performing a photo-lithography process and an etch process. A conductive material is deposited thereon. A planarization process is performed by a chemical mechanical polishing process. A polysilicon layer for control gate is exposed by performing an etch back process. A silicide layer(118A) is formed on the gate pattern(120) and the common source line.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，以简化制造工艺，减小层间电介质的厚度，并提高半导体器件的速度特性。 构成：在半导体衬底（100）上形成栅极图案（120）。 通过使用毯式方法在包括栅极图案（120）的半导体衬底（100）上形成抛光停止器（114）。 包括层间电介质（116）的多层沉积在栅极图案（120）上。 通过进行光刻工艺和蚀刻工艺，部分地蚀刻层间电介质（116），抛光停止器（114）和公共源极线形成区域的栅极氧化物层。 导电材料沉积在其上。 平面化处理通过化学机械抛光工艺进行。 用于控制栅极的多晶硅层通过执行回蚀工艺而被曝光。 在栅极图案（120）和公共源极线上形成硅化物层（118A）。

公开(公告)号：KR1020020009674A

公开(公告)日：2002-02-02

申请号：KR1020000043008

申请日：2000-07-26

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  김경현

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: PURPOSE: A trench isolation method for a semiconductor integrated circuit is provided to guarantee a field recess margin and to control pitting of a pad oxide layer even after a polysilicon layer and the pad oxide layer under the polysilicon layer are eliminated, by using the polysilicon layer as a polishing stop layer so that an oxide layer spacer is formed on the inner wall of a trench and on the sidewall of the polysilicon layer, and by using an etch-back process in removing the polysilicon layer. CONSTITUTION: The polysilicon layer is formed on a semiconductor substrate(110) having the pad oxide layer. A predetermined portion of the polysilicon layer, a predetermined portion of the pad oxide layer and the semiconductor substrate are sequentially etched to form the trench in the semiconductor substrate. A thermal oxide process is performed to form an oxide layer spacer on the inner wall of the trench and on the sidewall of the etched polysilicon layer. A nitride liner is formed on the resultant structure having the oxide layer spacer. A semiconductor device in which the inside of the trench having the oxide layer spacer is filled with an insulation material is planarized. The polysilicon layer is dry-etched while selectivity between the oxide layer spacer and the nitride liner is maintained at 1:1.

Abstract translation: 目的：提供一种用于半导体集成电路的沟槽隔离方法，以便即使在消除多晶硅层之后的多晶硅层和衬垫氧化物层之后，通过使用多晶硅层来确保场凹陷边缘并且控制焊盘氧化物层的点蚀 作为抛光停止层，使得在沟槽的内壁和多晶硅层的侧壁上形成氧化物隔离层，并且通过使用蚀刻工艺去除多晶硅层。 构成：多晶硅层形成在具有衬垫氧化物层的半导体衬底（110）上。 依次蚀刻多晶硅层的预定部分，衬垫氧化物层的预定部分和半导体衬底，以在半导体衬底中形成沟槽。 进行热氧化处理以在沟槽的内壁和蚀刻的多晶硅层的侧壁上形成氧化物层间隔物。 在具有氧化物层间隔物的所得结构上形成氮化物衬垫。 将其中填充有绝缘材料的具有氧化物层隔离物的沟槽的内部的半导体器件平坦化。 干蚀刻多晶硅层，同时氧化层间隔层和氮化物衬垫之间的选择性保持在1:1。

公开(公告)号：KR1020000025003A

公开(公告)日：2000-05-06

申请号：KR1019980041866

申请日：1998-10-07

Applicant: 삼성전자주식회사

Inventor： 김경현

IPC: H01L21/304

CPC classification number: B24B37/11 ,  H01L21/30625 ,  H01L21/31055

Abstract: PURPOSE: A polishing pad is provided to uniformly polish an entire semiconductor substrate through a control a polishing amount by establishing an area formed with holes or grooves in different conditions on a polishing face. CONSTITUTION: A polishing face polishes a surface of a semiconductor substrate to leave slurry. A first polishing face area(103) has a plurality of first parts containing the slurry with a first volume ratio with respect to a unit area of the polishing face and the plurality of first parts are formed in a first depth, a first width, and a first mutual distance(157) on the polishing face. A second polishing face area(105) has a plurality of second parts containing the slurry with a second volume ratio with respect to a unit area of the polishing area different from the first volume ratio and the second parts are formed in a second depth, a second width, and a second mutual distance(127).

Abstract translation: 目的：提供抛光垫，通过在抛光面上建立形成有不同条件的孔或凹槽的区域，通过控制抛光量对整个半导体基板进行均匀抛光。 构成：抛光面抛光半导体衬底的表面以留下浆料。 第一抛光面区域（103）具有多个第一部分，其包含相对于研磨面的单位面积具有第一体积比的浆料，并且多个第一部分形成为第一深度，第一宽度和 在抛光面上的第一相互距离（157）。 第二抛光面区域（105）具有多个第二部分，其包含相对于与第一体积比不同的抛光区域的单位面积具有第二体积比的浆料，并且第二部分形成为第二深度， 第二宽度和第二相互距离（127）。

公开(公告)号：KR1019990085616A

公开(公告)日：1999-12-15

申请号：KR1019980018164

申请日：1998-05-20

Applicant: 삼성전자주식회사

Inventor： 김경현 ,  이계헌 ,  박승범 ,  송장근

IPC: G02F1/136 ,  G02F1/1337 ,  G02F1/1343

Abstract: 컬러 필터 기판의 공통 전극 위에 화소 영역의 가운데에서 꺾어진 톱니 모양의 돌기를 형성하고, 박막 트랜지스터 기판의 화소 전극 위에 컬러 필터 기판 위의 돌기와 평행하게 교대로 톱니 모양의 돌기를 형성한다. 두 전극 위에는 톱니 모양 돌기의 꺾인 부분으로부터 반대쪽 기판 위의 돌기를 향하는 방향으로 가지 돌기를 형성하고, 공통 전극 위에 화소 전극의 경계와 박막 트랜지스터 기판의 돌기가 만나는 부분에서 화소 전극의 경계 쪽으로 연장되는 가지 돌기를 형성한다. 이렇게 하면, 전계가 인가되었을 때 하나의 화소 내에서 액정 분자의 배향 방향이 서로 다른 네 개의 영역을 얻을 수 있어 넓은 시야각을 확보할 수 있고, 대부분의 영역에서 돌기는 직선으로 형성되고 돌기가 꺾이는 부분에서도 둔각을 이루게 되어 빠른 응답 속도를 가지면서 액정 분자의 배향이 흐트러지는 경우에 발생하는 전경(disclination)을 없앨 수 있어 액정 표시 장치의 휘도를 향상시킬 수 있다.

公开(公告)号：KR1019990079440A

公开(公告)日：1999-11-05

申请号：KR1019980012067

申请日：1998-04-06

Applicant: 삼성전자주식회사

Inventor： 김경현

IPC: H04M19/00

Abstract: 무선 전화기의 휴대장치에서 고정장치로부터 수신되는 신호의 세기(전계 강도)를 검출하여 그 고정장치와의 거리를 판단하고, 근거리일 때에는 무선주파수 전력 레벨을 줄임으로써 통화 성능에 영향을 주지 않고 휴대장치의 배터리 전류 소모를 줄임을 특징으로 한다.