公开(公告)号：KR1020090016152A

公开(公告)日：2009-02-13

申请号：KR1020070080598

申请日：2007-08-10

Applicant: 삼성전자주식회사

Inventor： 이정현 ,  이창수 ,  이명재 ,  전찬봉 ,  박영수

IPC: H01L27/108 ,  H01L27/115

CPC classification number: H01L27/2409 ,  G11C13/0004 ,  H01L27/10847 ,  H01L27/2436

Abstract: A method for forming a nickel oxide layer and a method for manufacturing a resistive memory device including the nickel oxide layer are provided to obtain the nickel oxide layer with uniform oxidation state by using CVD or ALD(Atomic Layer Deposition) process. A nickel oxide layer is formed by using a CVD(Chemical Vapor Deposition) method. The source gas including a precursor of Ni is supplied to a reaction chamber(100) on which a substrate is loaded. The reaction gas including oxygen is supplied to the chamber. The precursor of the Ni is the anoxic precursor. The precursor of the Ni in the substrate(120) reacts to the reaction gas(30). The reaction gas decomposes the Ni(EtCp)2 into Ni and (EtCp)2. The (EtCp)2 is volatilized and the Ni is oxidized and is adhered to the upper surface of the substrate. A nickel oxide layer(200) is formed on the substrate. The precursor of the Ni is Ni(EtCp)2. The O2 gas is used as the reaction gas. The temperature of the substrate is 250 to 400 degrees centigrade when forming the nickel oxide layer.

Abstract translation: 提供了一种形成氧化镍层的方法和一种制造包括该氧化镍层的电阻式存储器件的方法，以通过使用CVD或ALD（原子层沉积）工艺获得具有均匀氧化态的氧化镍层。 通过使用CVD（化学气相沉积）法形成氧化镍层。 将包含Ni的前体的源气体供给到其上装载有基板的反应室（100）。 包括氧的反应气体被供应到室。 Ni的前体是缺氧前体。 衬底（120）中的Ni的前体与反应气体（30）反应。 反应气体将Ni（EtCp）2分解成Ni和（EtCp）2。 （EtCp）2挥发，Ni被氧化并附着在基板的上表面。 在基板上形成氧化镍层（200）。 Ni的前体是Ni（EtCp）2。 使用O 2气体作为反应气体。 当形成氧化镍层时，基板的温度为250〜400摄氏度。

公开(公告)号：KR1020080114357A

公开(公告)日：2008-12-31

申请号：KR1020070063826

申请日：2007-06-27

Applicant: 삼성전자주식회사

Inventor： 김선일 ,  송이헌 ,  박영수 ,  강동훈 ,  김창정 ,  박재철

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A thin film transistor is provided to obtain a high switching characteristic and increase an operation speed by using a transition metal doped IZO layer as a channel layer of the thin film transistor. A thin film transistor includes a gate electrode(140), a channel layer(110), a source electrode(120a) and a drain electrode(120b). The gate electrode and the channel layer are formed to interpose a gate insulating layer. The source electrode and the drain electrode are contacted with both ends of the channel layer. The channel layer includes the transition metal doped IZO(Indium Zinc Oxide).

Abstract translation: 提供薄膜晶体管以获得高开关特性，并且通过使用掺杂过渡金属的IZO层作为薄膜晶体管的沟道层来提高操作速度。 薄膜晶体管包括栅电极（140），沟道层（110），源电极（120a）和漏电极（120b）。 形成栅电极和沟道层以插入栅极绝缘层。 源电极和漏电极与沟道层的两端接触。 沟道层包括掺杂过渡金属的IZO（氧化铟锌）。

公开(公告)号：KR1020080106148A

公开(公告)日：2008-12-04

申请号：KR1020080104272

申请日：2008-10-23

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  김창정 ,  김선일 ,  송이헌 ,  박영수

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/78693 ,  H01L29/458

Abstract: A thin film transistor is provided to increase the stability and secure the device characteristic without the compensating circuit by forming the source and drain with the conductive oxide materials and the metal layer with low resistance. A thin film transistor comprises the gate(42), the gate isolation layer(44), the channel layer(46), the source(52a), and the drain(52b). The gate isolation layer is contacted with the gate. The channel layer is contacted with the gate isolation layer. The channel layer is in opposite directions to the gate. The gate isolation layer is positioned between the channel layer and the gate. The source is contacted with one end of the channel layer. The drain is contacted with the other end of the channel layer. The channel layer is the amorphous oxide semiconductor layer. The source and the drain are formed by including the conductive oxide layer and the metal layer with low resistance.

Abstract translation: 提供薄膜晶体管以通过用导电氧化物材料和具有低电阻的金属层形成源极和漏极来增加稳定性并且确保器件特性而不需要补偿电路。 薄膜晶体管包括栅极（42），栅极隔离层（44），沟道层（46），源极（52a）和漏极（52b）。 栅极隔离层与栅极接触。 沟道层与栅极隔离层接触。 沟道层与栅极相反。 栅极隔离层位于沟道层和栅极之间。 源与通道层的一端接触。 漏极与沟道层的另一端接触。 沟道层是非晶氧化物半导体层。 源极和漏极通过包括导电氧化物层和具有低电阻的金属层而形成。

公开(公告)号：KR1020080094300A

公开(公告)日：2008-10-23

申请号：KR1020070038537

申请日：2007-04-19

Applicant: 삼성전자주식회사

Inventor： 박재철 ,  김창정 ,  김선일 ,  송이헌 ,  박영수

IPC: H01L29/786 ,  G02F1/136

CPC classification number: H01L29/78618 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor is provided to guarantee a uniformity characteristic of a flat panel display by using a thin film transistor in a flat panel display like an LCD(liquid crystal display) or an OLED(organic light emitting diode) wherein the channel layer of the thin film transistor is an amorphous oxide semiconductor layer. A gate insulation layer(44) comes in contact with a gate. A channel layer(46) confronts the gate wherein the gate insulation layer is positioned between the gate and the channel layer, coming in contact with the gate insulation layer. A source(52a) comes in contact with one end of the channel layer. A drain(52b) comes in contact with the other end of the channel layer. The channel layer is an amorphous oxide semiconductor layer. The source and the drain are a conductive oxide layer in which predetermined conductive impurities are included in an oxide semiconductor layer. Low resistance metal layers can be formed on the source and the drain. The gate can be formed on or under the channel layer.

Abstract translation: 提供薄膜晶体管以通过在诸如LCD（液晶显示器）或OLED（有机发光二极管）的平板显示器中使用薄膜晶体管来保证平板显示器的均匀性特性，其中， 薄膜晶体管是非晶氧化物半导体层。 栅极绝缘层（44）与栅极接触。 沟道层（46）面对栅极，其中栅极绝缘层位于栅极和沟道层之间，与栅极绝缘层接触。 源（52a）与沟道层的一端接触。 漏极（52b）与沟道层的另一端接触。 沟道层是非晶氧化物半导体层。 源极和漏极是在氧化物半导体层中包含预定导电杂质的导电氧化物层。 低电阻金属层可以形成在源极和漏极上。 栅极可以形成在沟道层上或下面。

公开(公告)号：KR1020080086759A

公开(公告)日：2008-09-26

申请号：KR1020070028861

申请日：2007-03-23

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  박영수 ,  이창범

IPC: H01L27/115

CPC classification number: H01L27/101 ,  H01L27/24 ,  H01L27/2463 ,  H01L21/28273

Abstract: A non-volatile memory device having a threshold switching resistor, a memory array having the memory device, and a method of manufacturing the memory device are provided to simplify a structure of a cross-point memory array by using a resistor layer with a threshold switching property as a switching element. A non-volatile memory device includes a first electrode(12), a first resistor(14), a second electrode(16), a second resistor(18), and a third electrode(22). The first resistor is formed on the first electrode and has a threshold switching property. The second electrode is formed on the first resistor. The second resistor is formed on the second electrode and has more than two resistances. The third electrode is formed on the second resistor. The first resistor is made of NiO. The second resistor is made of at least one material selected from the group consisting of NiO, TiO2, Al2O3, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.

Abstract translation: 提供具有阈值开关电阻器的非易失性存储器件，具有存储器件的存储器阵列和制造存储器件的方法，以通过使用具有阈值切换的电阻层来简化交叉点存储器阵列的结构 属性作为开关元件。 非易失性存储器件包括第一电极（12），第一电阻器（14），第二电极（16），第二电阻器（18）和第三电极（22）。 第一电阻器形成在第一电极上并具有阈值切换特性。 第二电极形成在第一电阻器上。 第二电阻器形成在第二电极上并且具有两个以上的电阻。 第三电极形成在第二电阻器上。 第一个电阻由NiO制成。 第二电阻器由选自NiO，TiO 2，Al 2 O 3，HfO，ZrO，ZnO，WO 3，CoO和Nb 2 O 5中的至少一种材料制成。

公开(公告)号：KR100858088B1

公开(公告)日：2008-09-10

申请号：KR1020070020528

申请日：2007-02-28

Applicant: 삼성전자주식회사

Inventor： 강동훈 ,  겐리치스테파노비치 ,  송이헌 ,  박영수 ,  김창정

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: 박막 트랜지스터 및 그 제조 방법에 관해 개시되어 있다. 개시된 본 발명은 게이트, 채널층, 소오스 및 드레인을 포함하는 박막 트랜지스터에 있어서, 상기 소오스 및 드레인은 금속으로 이루어지고 상기 채널층과 상기 소오스 및 드레인 사이에 금속 산화물층이 구비되어 있고, 상기 소오스 및 드레인과 상기 채널층은 상기 금속 산화물층에 접촉된 것을 특징으로 하는 박막 트랜지스터를 제공한다. 상기 금속 산화물층은 층내에 금속 함량 기울기를 가질 수 있다.

公开(公告)号：KR100837280B1

公开(公告)日：2008-06-11

申请号：KR1020070024094

申请日：2007-03-12

Applicant: 삼성전자주식회사

Inventor： 박영수 ,  김영남 ,  임영삼 ,  김기정 ,  강필규

IPC: H01L21/00

CPC classification number: H01L21/3221 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device having a gettering region and a manufacturing method thereof are provided to improve integration density of the semiconductor device by minimizing a metal contamination of an IC formed on a semiconductor layer. A semiconductor device includes a semiconductor substrate(100), an insulation layer(150), a device semiconductor layer(200), and at least one gettering region(165). The insulation layer is arranged on the semiconductor substrate. The device semiconductor layer is arranged on the insulation layer. The gettering region includes plural sites for capturing metal elements in the device semiconductor layer. The gettering region is arranged in the insulation layer. The gettering region is arranged in a charge semiconductor pattern inside the insulation layer. The charge semiconductor pattern is contacted with a lower surface of the device semiconductor layer.

Abstract translation: 提供具有吸杂区域的半导体器件及其制造方法，以通过使形成在半导体层上的IC的金属污染最小化来提高半导体器件的集成密度。 半导体器件包括半导体衬底（100），绝缘层（150），器件半导体层（200）和至少一个吸杂区域（165）。 绝缘层设置在半导体衬底上。 器件半导体层布置在绝缘层上。 吸气区域包括用于捕获器件半导体层中的金属元素的多个位置。 吸气区域布置在绝缘层中。 吸气区域设置在绝缘层内部的电荷半导体图案中。 电荷半导体图案与器件半导体层的下表面接触。

公开(公告)号：KR1020080019331A

公开(公告)日：2008-03-04

申请号：KR1020060081466

申请日：2006-08-28

Applicant: 삼성전자주식회사

Inventor： 박영수 ,  조규철 ,  강태수 ,  최삼종

IPC: H01L21/76

Abstract: An isolation method of a semiconductor device is provided to reduce an influence of electric charges in an interface between silicon and an oxide layer by suppressing a leakage current. A trench(106) is formed on a semiconductor wafer(100). An oxide layer pattern(116a,118a) is formed to bury the trench. Nonmetal ions are implanted into the oxide layer pattern to form a gettering region(112a). The gettering region is formed apart from an upper surface of the oxide layer pattern and the trench. The gettering region is formed to collect impurities from the inside of the oxide layer pattern. The nonmetal ions include one selected from a group including H, He, B, C, N, O, Si, Ar, and Ge. The gettering region has a thickness of 1200 to 1800 Š.

Abstract translation: 提供半导体器件的隔离方法，通过抑制漏电流来减少硅与氧化物层之间的界面中的电荷的影响。 沟槽（106）形成在半导体晶片（100）上。 形成氧化物层图案（116a，118a）以埋入沟槽。 将非金属离子注入到氧化物层图案中以形成吸气区域（112a）。 吸气区域形成为与氧化物层图案和沟槽的上表面分开。 吸气区形成为从氧化物层图案的内部收集杂质。 非金属离子包括选自H，He，B，C，N，O，Si，Ar和Ge中的一种。 吸气区的厚度为1200至1800Š。

公开(公告)号：KR1020080010621A

公开(公告)日：2008-01-31

申请号：KR1020060070884

申请日：2006-07-27

Applicant: 삼성전자주식회사

Inventor： 후아샹잉 ,  박영수 ,  선우문욱 ,  조세영

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A method for forming a poly-Si pattern, a multi-layer cross point resistive memory device including the poly-Si pattern and a method for manufacturing the same are provided to improve an operation characteristic of the multi-layer cross point resistive memory device using a poly-Si diode. A multi-layer cross point resistive memory device includes a wire(M), a first vertical diode(D1), a first bottom electrode(BE1), a first lamination pattern(P1), a second vertical diode(D2), a second bottom electrode(BE2), and a second lamination pattern(P2). The wire is formed on a semiconductor substrate. The first vertical diode is formed on the wire and is made of polysilicon. The first bottom electrode is formed on the first vertical diode. The first lamination pattern is formed on the first bottom electrode perpendicular to the wire. The first lamination pattern has a structure in which a first resistor and a first top electrode are sequentially laminated. The second vertical diode is formed on the first lamination pattern and is made of the polysilicon. The second bottom electrode is formed on the second vertical diode. The second lamination pattern is formed on the second bottom electrode perpendicular to the first lamination pattern. The second lamination pattern has a structure in which a second resistor and a second top electrode are sequentially laminated.

Abstract translation: 提供一种形成多晶硅图案的方法，包括多晶硅图案的多层交叉点电阻式存储器件及其制造方法，以改善使用多层交叉点电阻式存储器件的工作特性 多晶硅二极管。 多层交叉点电阻式存储器件包括线（M），第一垂直二极管（D1），第一底电极（BE1），第一叠层图案（P1），第二垂直二极管（D2），第二 底部电极（BE2）和第二层压图案（P2）。 导线形成在半导体基板上。 第一垂直二极管形成在导线上并由多晶硅制成。 第一底部电极形成在第一垂直二极管上。 第一层叠图案形成在垂直于线的第一底部电极上。 第一层叠图案具有顺序层叠第一电阻器和第一顶部电极的结构。 第二垂直二极管形成在第一层叠图案上并由多晶硅制成。 第二底部电极形成在第二垂直二极管上。 第二层叠图案形成在与第一层叠图案垂直的第二底部电极上。 第二层压图案具有顺序层叠第二电阻器和第二顶部电极的结构。

公开(公告)号：KR1020070117748A

公开(公告)日：2007-12-13

申请号：KR1020060051763

申请日：2006-06-09

Applicant: 삼성전자주식회사

Inventor： 최삼종 ,  강태수 ,  박영수 ,  김연숙 ,  이윤희 ,  조규철

IPC: H01L21/304

Abstract: A CVD(chemical vapor deposition) apparatus is provided to identically or similarly polish the center and edge of a wafer by including a plate in which the cushion applied to a polishing pad corresponding to the edge of the wafer is smaller than the cushion applied a polishing pad corresponding to the center of the wafer. A polishing head(112) pressurizes and rotates the back surface of a wafer. A polishing pad(114) polishes the front surface of the wafer, confronting the polishing head. A plate(116) rotates in the same/opposite direction as/to the polishing head. The cushion of the polishing pad applied to the center and edge of the wafer is different in the plate so that the center and edge of the wafer positioned on the polishing pad are polished identically or similarly. The plate includes a hard part and a soft part surrounding the hard part. In the hard part, the polishing pad corresponding to the center of the wafer has a predetermined compression strength or higher. In the soft part, the polishing pad corresponding to the edge of the wafer has lower compression strength than that of the hard part.

Abstract translation: 提供CVD（化学气相沉积）设备以通过包括一个板来对晶片的中心和边缘进行相同或相似的抛光，其中施加到与晶片边缘相对应的抛光垫的衬垫小于衬垫施加的抛光 垫对应于晶片的中心。 抛光头（112）对晶片的背面进行加压和旋转。 抛光垫（114）抛光晶片的前表面，面对抛光头。 板（116）沿与抛光头相同/相反的方向旋转。 施加到晶片的中心和边缘的抛光垫的衬垫在板中是不同的，使得位于抛光垫上的晶片的中心和边缘被相同地或类似地抛光。 该板包括硬质部分和围绕硬质部分的软质部分。 在硬质部分中，与晶片中心对应的抛光垫具有预定的压缩强度或更高的压缩强度。 在软部分中，与晶片边缘相对应的抛光垫具有比硬部分低的压缩强度。