公开(公告)号：KR100065557B1

公开(公告)日：1993-09-15

申请号：KR1019900014001

申请日：1990-09-05

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  주태식 ,  김영철 ,  이석정

IPC: H03M13/00 ,  G06F11/10

公开(公告)号：KR100064097B1

公开(公告)日：1993-08-04

申请号：KR1019900002072

申请日：1990-02-20

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  김영철 ,  이석정 ,  유중재

IPC: G11C17/00

公开(公告)号：KR1020110015934A

公开(公告)日：2011-02-17

申请号：KR1020090073390

申请日：2009-08-10

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  조성래 ,  김익수 ,  임동현 ,  신희주 ,  조은희

IPC: H01L27/115 ,  G11C13/02 ,  G11C16/00

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/101 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: PURPOSE: A non-volatile memory device and a method for programming the same are provided to obtain a cell unit with a multi-level without the increase of a chip-size. CONSTITUTION: A first electrode(142) is formed on the upper side of a substrate. A first phase change material pattern(144) is formed on the first electrode. A second phase change material pattern(152) is formed on the first phase change material pattern. A second electrode(154) is formed on the second phase change material pattern. The volume of the second phase change material pattern is larger than the volume of the first phase change material pattern.

Abstract translation: 目的：提供非易失性存储器件及其编程方法，以获得具有多级的单元单元，而不增加芯片尺寸。 构成：第一电极（142）形成在基板的上侧。 第一相变材料图案（144）形成在第一电极上。 在第一相变材料图案上形成第二相变材料图案（152）。 第二电极（154）形成在第二相变材料图案上。 第二相变材料图案的体积大于第一相变材料图案的体积。

公开(公告)号：KR1020090010427A

公开(公告)日：2009-01-30

申请号：KR1020070073521

申请日：2007-07-23

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  안동호 ,  임영수 ,  하용호 ,  장준영 ,  임동원

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L45/06 ,  H01L21/31051 ,  H01L21/3213 ,  H01L21/76897 ,  H01L27/2409 ,  H01L45/1233

Abstract: A phase change memory device is provided to reduce current applied in reset action and overcome patterning limit and implement phase change memory device which is good for high integration. A substrate in which bottom patterns are equipped is formed. Bottom electrodes of a linear type or a L type are contacted to bottom patterns on the substrate mounting the bottom patterns and are equipped with an upper side having x-axis and y-axis. Phase change patterns are contacted to the upper side of the bottom electrodes and have the respective wider width than the x-axis and y-axis. Upper electrodes are arranged on the phase change patterns.

Abstract translation: 提供相变存储器件以减少复位动作中施加的电流并克服图案化限制并实现有利于高集成度的相变存储器件。 形成有底部图案的基板。 直线型或L型的底部电极与安装底部图案的基板上的底部图案接触，并配备有具有x轴和y轴的上侧。 相变图案与底部电极的上侧接触并且具有相对于x轴和y轴宽度宽的宽度。 上电极配置在相变图案上。

公开(公告)号：KR1020090006628A

公开(公告)日：2009-01-15

申请号：KR1020070070153

申请日：2007-07-12

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  안동호 ,  이겨레 ,  박준상 ,  고한봉 ,  박영림

IPC: H01L27/115

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/141

Abstract: A phase change memory device and a manufacturing method thereof are provided to reduce a current supplied in reset operation by reducing interface dimensions between a phase change pattern and a bottom electrode in which joule heat is generated. Bit lines(BL) are parallel arranged with a vertical direction. Word lines(WL) are parallel arranged with a horizontal direction. The bit lines intersect with the word lines. Each phase change pattern(Rp) is arranged on an intersection of the bit lines and the word lines. Each diode(D) is serially connected to one corresponding to each phase change pattern. Each phase change pattern is connected to one corresponding to each bit line. Each diode is connected to one corresponding to each word line.

Abstract translation: 提供了一种相变存储器件及其制造方法，通过减少产生焦耳热的相变图案和底部电极之间的界面尺寸来减少复位操作中提供的电流。 位线（BL）与垂直方向平行排列。 字线（WL）与水平方向平行排列。 位线与字线相交。 每个相变模式（Rp）被布置在位线和字线的交叉点上。 每个二极管（D）串联连接到一个对应于每个相变图案。 每个相变模式连接到对应于每个位线的一个。 每个二极管连接到一个对应于每个字线的二极管。

公开(公告)号：KR100766499B1

公开(公告)日：2007-10-15

申请号：KR1020060102569

申请日：2006-10-20

Applicant: 삼성전자주식회사

Inventor： 안동호 ,  호리이 ,  신종찬 ,  배준수 ,  안형근

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/143 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  Y10S438/90

Abstract: A phase change memory device and a fabricating method thereof are provided to prevent defects of a phase-change material by contacting two terminals connected to a phase-change pattern with a lower surface of the phase-change pattern. A mold insulating layer is formed on a semiconductor substrate, and a first plug electrode(160) and a second plug electrode(161) are formed in the mold insulating layer. A phase-change pattern(165) is disposed on the mold insulating layer, and is connected to an upper surface of the first plug electrode and a first portion of an upper surface of the second plug electrode. The entire surface of the substrate is covered by an upper insulating layer. A wiring plug(190) is connected to a second portion of the upper surface of the second plug electrode through the upper insulating layer. A wiring is disposed on the upper insulating layer.

Abstract translation: 提供一种相变存储器件及其制造方法，通过使与相变图案相连的两个端子与相变图案的下表面接触来防止相变材料的缺陷。 在半导体衬底上形成模具绝缘层，在模具绝缘层中形成第一插头电极（160）和第二插头电极（161）。 相变图案（165）设置在模具绝缘层上，并且连接到第一插头电极的上表面和第二插头电极的上表面的第一部分。 基板的整个表面被上绝缘层覆盖。 布线插头（190）通过上绝缘层连接到第二插头电极的上表面的第二部分。 布线布置在上绝缘层上。

公开(公告)号：KR1019950009765B1

公开(公告)日：1995-08-28

申请号：KR1019920016857

申请日：1992-09-16

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  이석정

IPC: G06F17/00

Abstract: a first adder for adding input data and a coefficient; a second adder for adding the input data and an inverted value of the coefficient; first and second absolute value circuits for respectively outputting absolute values for the outputs of the first and second adders; first and second memories for addressing output values from the first and second absolute value circuits and for memorizing the addressed values as data values; and a third adder for adding an output of the first memory and an inverted value of an output from the second memory.

Abstract translation: 用于添加输入数据和系数的第一加法器; 第二加法器，用于将输入数据和系数的反相值相加; 用于分别输出第一和第二加法器的输出的绝对值的第一和第二绝对值电路; 第一和第二存储器，用于寻址来自第一和第二绝对值电路的输出值，以及将所寻址的值存储为数据值; 以及第三加法器，用于将第一存储器的输出和来自第二存储器的输出的反相值相加。

公开(公告)号：KR1019940001589B1

公开(公告)日：1994-02-25

申请号：KR1019910015669

申请日：1991-09-09

Applicant: 삼성전자주식회사

Inventor： 김석기 ,  안형근 ,  주태식 ,  이석정

IPC: G06F12/02

Abstract: The digital data storage for digital audio system includes a data storage device which stores and reads out data. A digital signal processor operates on a digital signal from the data storage device, and an interface, between the data storage and processor, drives and buffers the read-out data. A system control microcomputer controls the digital signal processor, and a memory connected to the processor is capable of reading and writing data. A main computer monitors the data stored in the memory, and an interface portion, between the memory and main computer, interfaces the data.

Abstract translation: 用于数字音频系统的数字数据存储器包括存储和读出数据的数据存储装置。 数字信号处理器对来自数据存储设备的数字信号进行操作，并且数据存储器和处理器之间的接口驱动并缓冲读出的数据。 系统控制微机控制数字信号处理器，连接到处理器的存储器能够读取和写入数据。 主计算机监视存储器中存储的数据，存储器和主计算机之间的接口部分接口数据。

公开(公告)号：KR100065579B1

公开(公告)日：1993-09-15

申请号：KR1019900021950

申请日：1990-12-27

Applicant: 삼성전자주식회사

Inventor： 이만영 ,  박학송 ,  안형근 ,  이석정 ,  염홍렬 ,  최용진

IPC: G06F11/10

公开(公告)号：KR1019930002854B1

公开(公告)日：1993-04-12

申请号：KR1019900021950

申请日：1990-12-27

Applicant: 삼성전자주식회사

Inventor： 이만영 ,  박학송 ,  안형근 ,  이석정 ,  염홍렬 ,  최용진

IPC: G06F11/10

Abstract: The method calculates error values with a simple circuit of a little delay to correct error. The apparatus includes the 1st adder (110) for correcting the error in received data by adding the error value (Y1 or Y2) from a buffer memory (101) to the data received from a buffer memory section (100), an error discriminator (100) for detecting error, and a controlling section (190) for controlling overall operation of the apparatus.

Abstract translation: 该方法用简单的延迟电路计算误差值，以纠正错误。 该装置包括第一加法器（110），用于通过将来自缓冲存储器（101）的误差值（Y1或Y2）与从缓冲存储器部分（100）接收的数据相加来校正接收数据中的误差，误差鉴别器（ 100），以及用于控制装置的整体操作的控制部（190）。