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公开(公告)号：KR1020080091980A
公开(公告)日：2008-10-15
申请号：KR1020070035176
申请日：2007-04-10
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L23/525 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2924/01049
Abstract: A chip stack package and a method of fabricating the same are provided to bond wires easily and reduce thickness of the package by placing a pad in a scribe region and depositing unit semiconductor chips with different sizes on active surfaces. A chip stack package(200) comprises a substrate(210), unit semiconductor chips(260), a plurality of connecting members, and a sealing part(280). The unit semiconductor chips are installed with a plurality of semiconductor chips(240,250) having a plurality of pads on active surfaces. The connecting members connect the semiconductor chips with circuit patterns of the substrate. The sealing part coats the unit semiconductor chips and the connecting members. The semiconductor chips have different sizes. One of the semiconductor chips is installed with a plurality of first pads(243) which are arranged in a first chip region, and the other of the semiconductor chips is installed with a plurality of second pads(253) which are arranged in a scribe region. The connecting members are wires(270,275).
Abstract translation: 提供一种芯片堆叠封装及其制造方法，通过将焊盘放置在刻划区域中并且在活性表面上沉积具有不同尺寸的单元半导体芯片，从而容易地接合线并减小封装的厚度。 芯片堆叠封装（200）包括衬底（210），单元半导体芯片（260），多个连接构件和密封部分（280）。 单元半导体芯片安装有多个在有源表面上具有多个焊盘的半导体芯片（240,250）。 连接构件将半导体芯片与基板的电路图案连接。 密封部分涂覆单元半导体芯片和连接构件。 半导体芯片具有不同的尺寸。 半导体芯片之一安装有布置在第一芯片区域中的多个第一焊盘（243），并且另一个半导体芯片安装有多个第二焊盘（253），其布置在划线区域 。 连接构件是导线（270,275）。
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公开(公告)号：KR100843240B1
公开(公告)日：2008-07-03
申请号：KR1020070028864
申请日：2007-03-23
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L21/76898 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/11462 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/0106 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19043 , H01L2224/05552
Abstract: A semiconductor device for wafer level stack and a method for manufacturing a through electrode thereof are provided to reduce a manufacturing cost by forming a through electrode before forming a last metal layers on a wafer. An integrated circuit unit is formed on a wafer. A via hole for through electrode is formed on the integrated circuit unit of the wafer(S110). A passivation layer is formed to cover an entire surface of the wafer including the via hole for through electrode(S150). A final metal layer pattern is formed on the wafer including the via hole for through electrode. The integrated circuit unit performs a memory function. The via hole for through electrode is formed after a lower metal layer pattern for bonding pad is formed on the integrated circuit unit.
Abstract translation: 提供了一种用于晶片级堆叠的半导体器件及其通孔的制造方法，以在晶片上形成最后的金属层之前形成通孔来降低制造成本。 在晶片上形成集成电路单元。 在晶片的集成电路单元上形成用于贯通电极的通孔（S110）。 形成钝化层以覆盖包括用于通孔的通孔的晶片的整个表面（S150）。 在包括用于通孔的通孔的晶片上形成最终的金属层图案。 集成电路单元执行存储功能。 在集成电路单元上形成用于焊盘的下层金属层图案之后，形成贯通电极用通孔。
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33.发明授权웨이퍼 레벨 칩 스케일 패키지, 그 제조 방법, 및 웨이퍼레벨 칩 스케일 패키지를 포함하는 반도체 칩 모듈 有权WAFER LEVEL CHIP SCALE包装及其制造方法，以及半导体芯片模块，包括WAFER LEVEL CHIP SCALE包装
公开(公告)号：KR100817079B1
公开(公告)日：2008-03-26
申请号：KR1020060122587
申请日：2006-12-05
Applicant: 삼성전자주식회사
CPC classification number: H01L23/525 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/05647 , H01L2224/05666 , H01L2224/11334 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
Abstract: A wafer level chip scale package is provided to induce the crack generated in a solder joint to a sacrificial metal layer by mounting a wafer level chip scale package on a module substrate so that a semiconductor chip module can be constructed. A semiconductor chip includes a bonding pad. A first insulation layer is formed on the semiconductor chip to expose the bonding pad. A redistribution line is formed on the exposed bonding pad and the first insulation layer. A sacrificial layer(230) is formed under a redistribution pad of the redistribution line. A second insulation layer is formed on the redistribution line to expose the redistribution line, including a crack inducing hole(245) formed at the side of the sacrificial layer. An external connection terminal is attached to the redistribution pad. The sacrificial layer can include a solder. The crack inducing hole can have a polygonal structure surrounding a partial surface of the external connection terminal.
Abstract translation: 提供晶片级芯片级封装以通过将晶片级芯片级封装安装在模块衬底上来引起在焊接接头中产生的牺牲金属层的裂纹，从而可构建半导体芯片模块。 半导体芯片包括接合焊盘。 在半导体芯片上形成第一绝缘层以露出焊盘。 在暴露的焊盘和第一绝缘层上形成再分配线。 牺牲层（230）形成在再分布线的再分布垫的下方。 在再分配线上形成第二绝缘层以暴露再分布线，包括在牺牲层侧形成的裂纹诱导孔（245）。 外部连接端子连接到再分配板。 牺牲层可以包括焊料。 裂纹诱导孔可以具有围绕外部连接端子的部分表面的多边形结构。
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公开(公告)号：KR1020070112655A
公开(公告)日：2007-11-27
申请号：KR1020060045814
申请日：2006-05-22
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L23/473 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
Abstract: A stack type semiconductor device having a cooling path is provided to cool the heat generated from a semiconductor chip through the cooling path, and to prevent a warpage problem by joining the bottom surfaces of semiconductor chips each other. A first and a second semiconductor chips(100,200) are joined facing a second surface each other. A circular type third cooling path(310) is formed at the center portion of the stack type semiconductor device(300) by a first cooling path within the first semiconductor chip and a second cooling path within the second semiconductor chip. If the stack type semiconductor device is installed within an electronic products having a cooling pan, a cooling air can be flowed directly through third cooling path. Thus, when operating the stack type semiconductor, the heat can be exhausted efficiently to the outside.
Abstract translation: 提供具有冷却路径的堆叠型半导体器件，以冷却通过冷却路径从半导体芯片产生的热量，并且通过将半导体芯片的底面彼此接合来防止翘曲问题。 第一和第二半导体芯片（100,200）彼此面对第二表面。 通过第一半导体芯片内的第一冷却路径和第二半导体芯片内的第二冷却路径，在堆叠型半导体器件（300）的中央部形成有圆形的第三冷却路径（310）。 如果堆叠式半导体器件安装在具有冷却盘的电子产品中，则可以通过第三冷却路径直接流动冷却空气。 因此，当操作堆叠型半导体时，可以将热量有效地排出到外部。
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公开(公告)号：KR1020070017796A
公开(公告)日：2007-02-13
申请号：KR1020050072389
申请日：2005-08-08
Applicant: 삼성전자주식회사
CPC classification number: H01L24/11 , H01L21/0273 , H01L23/49816 , H01L2224/03914 , H01L2924/01079
Abstract: 본 발명은 포토레지스트의 소모량을 줄이기 위하여 포토레지스트층의 높이를 낮추면서 원하는 체적의 범프를 형성하는 범프 형성 방법에 관한 것이다. 본 발명은 UBM층을 개방시키는 개구부를 형성하되 노광 초점이 초점심도(DOF; Depth Of Focus)를 벗어나도록 포커스 오프셋(focus offset)을 조정해주어 포토레지스트층 상면에서 소정 깊이까지 내경이 감소되도록 하여 경사면을 형성하는 노광 및 현상 단계, 개방된 UBM층으로부터 소정 높이까지 범프 하부 금속층을 형성하는 단계 및 포토레지스트층의 개구부에 의해 노출된 범프 하부 금속층 상에 범프를 형성하는 단계를 포함하는 반도체 장치용 범프 형성 방법을 제공한다. 이에 의하여 범프가 버섯형태(mushroom type)로 형성되어 상부에서 보다 많은 체적이 확보됨으로써 포토레지스트층의 높이를 낮출 수 있어 포토레지스트의 소모량이 감소될 수 있다.
범프, 솔더 볼, 금 범프, 버섯형, 플립 칩 본딩, 범프 본딩-
Patent Agency Ranking
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公开(公告)号：KR100574986B1
公开(公告)日：2006-04-28
申请号：KR1020040067094
申请日：2004-08-25
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2924/00014
Abstract: 플립 칩(flip chip) 접속을 위한 범프(bump)를 형성하는 방법을 제시한다. 본 발명에 따르면, 웨이퍼의 접촉 패드 상에 도금을 위한 시드(seed)층을 형성하고 그 상에 차폐층을 형성한 후, 감광성(photo sensitive)의 마스크층을 형성한다. 마스크층을 노광 및 현상하여 마스크 패턴을 형성하고, 노출된 차폐층 부분을 건식 식각(dry etch)으로 제거한다. 이에 따라, 노출되는 시드층 부분으로 도금 성장하여 범프(bump)를 형성한다.
플립 칩, 범프, 도금, 패드 용해, 이중 코팅-
公开(公告)号：KR1020040044606A
公开(公告)日：2004-05-31
申请号：KR1020020072673
申请日：2002-11-21
Applicant: 삼성전자주식회사
Inventor： 정현수
IPC: H01L21/02
Abstract: PURPOSE: An O-ring of semiconductor fabrication apparatus is provided to insert correctly the O-ring into a groove by forming a distinctive line on the O-ring. CONSTITUTION: An O-ring of semiconductor fabrication apparatus is formed at a connection part between a predetermined member and an assembly adhered on the predetermined member in order to encapsulate the predetermined member. The O-ring(2) is inserted into a groove, which is formed on an adhesive side of the assembly. A distinctive line(10) is formed on the O-ring in order to identify an insertion part inserted into the groove and the remaining part along an inner circumference and an outer circumference of the O-ring. The distinctive line is projected from the inner circumference and the outer circumference of the O-ring.
Abstract translation: 目的：提供半导体制造装置的O形环，通过在O形环上形成一条不同的线，将O形环正确插入槽中。 构成：半导体制造装置的O形环形成在预定构件和附着在预定构件上的组件之间的连接部分上，以封装预定构件。 O形环（2）插入到形成在组件的粘合剂侧上的凹槽中。 在O形环上形成有特殊的线（10），以便识别插入槽中的插入部分和沿着O形环的内圆周和外圆周的剩余部分。 独特的线从O形圈的内圆周和外圆周突出。
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