公开(公告)号：SG138522A1

公开(公告)日：2008-01-28

申请号：SG2007030810

申请日：2007-04-27

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  NGUYEN PHUNG T ,  WILLE WILLIAM C ,  LINSAY RICHARD ,  LUN ZHAO ,  FU CHONG YUNG ,  PANDA SIDDHARTHA

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

公开(公告)号：SG132585A1

公开(公告)日：2007-06-28

申请号：SG2006064562

申请日：2006-09-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SUNFEI FANG ,  JUNG KIM JUN ,  ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  WAY TEH YOUNG

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200 [err]C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

公开(公告)号：DE69302960D1

公开(公告)日：1996-07-11

申请号：DE69302960

申请日：1993-03-23

Applicant: IBM

Inventor： DOERRE GEORGE WILLIAM ,  OGURA SEIKI ,  ROVEDO NIVO

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L21/302

Abstract: An SOI wafer (10/20) has an epitaxial device layer (30) of initial thickness that is formed into a set of mesas (40) in the interval between which a temporary layer (42) of polysilicon is blanket deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop pads (45) (having a thickness greater than the initial thickness) except on the mesa side walls. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide forming pads (45) is not removed but serves both as an isolating layer to provide dielectric isolation between final mesas (40') in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

公开(公告)号：DE3688042T2

公开(公告)日：1993-09-16

申请号：DE3688042

申请日：1986-10-10

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SCHULZ RONALD N

IPC: G03F1/00 ,  G03F1/08 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00 ,  H01L21/76

公开(公告)号：DE3681696D1

公开(公告)日：1991-10-31

申请号：DE3681696

申请日：1986-07-29

Applicant: IBM

Inventor： BEYER KLAUS DIETRICH ,  MAKRIS JAMES STEVE ,  MENDEL ERIC ,  NUMMY KAREN ANN ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763

Abstract: A chemical-mechanical (chem-mech) method for removing SiO₂ protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si₃N₄ (29) is deposited onto the wafer surface, which is then chem-mech polished with a SiO₂ water based slurry. The Si₃N₄ acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si₃N₄ layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO₂ protuberances are removed to provide a substantially planar integrated structure.

公开(公告)号：CA1273274A

公开(公告)日：1990-08-28

申请号：CA508583

申请日：1986-05-07

Applicant: IBM

Inventor： BEYER KLAUS D ,  MAKRIS JAMES S ,  MENDEL ERIC ,  NUMMY KAREN A ,  OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/205

Abstract: A chemical-mechanical (chem-mech) method for removing SiO2 protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si3N4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO2 water based slurry. The Si3N4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si3N4 layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO2 protuberances are removed to provide a substantially planar integrated structure.

公开(公告)号：DE3474742D1

公开(公告)日：1988-11-24

申请号：DE3474742

申请日：1984-11-06

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/60

Abstract: Methods for producing integrated circuit structures are described with reference to a small area lateral bipolar transistor comprising a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of dielectric isolation. At least two narrow width PN junction regions are located within at least one of the surface regions. Substantially vertical conformal conductive layers (62, 64) electrically contact each of the PN junction regions which serve as the emitter (56) and collector (58) regions for the bipolar transistor. A junction base region (74) of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers (22) are in electrical contact with an edge of each of the vertical conductive layers (62, 64) and separated from the surface regions by a first electrically insulating layer (20). A second insulating layer (70) covers the conformal conductive layers. The horizontal conductive layer is patterned so as to form conductive lines electrically separated from one another. A third insulating layer (24) is located over the patterned horizontal conductive layers. An ohmic contact (80, 84) is made to each of the horizontal conductive layers (22) through an opening in the third insulating layer (24) which effectively makes electrical contacts to the emitter (56) and collector (58) regions via the patterned horizontal conductive layers (22) and the vertical conductive layers (62, 64). Another contact (82) is made to the base region (74) which contact is separated from the vertical conductive layers (62, 64) by the second insulating layer (70).