公开(公告)号：JP2001274262A

公开(公告)日：2001-10-05

申请号：JP2001044604

申请日：2001-02-21

Applicant: IBM

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A

IPC: H01L21/266 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET array where a high voltage device and a low voltage device are formed on the same substrate. SOLUTION: A method for forming a MOSFET array includes a step for preparing a substrate, a step for forming ac conductor layer on the substrate, a step for injecting dopant species into conductor layer, a step for counter- doping the non-mask part of the doped conductor layer and masking a part of the doped conductor layer and step for forming a depletion conductor region on the substrate. Thus, the substitute of dual gate oxide for MOSFET, in which a high voltage region in the counter-doped part is used for the memory array of DRAM, EDRAM, SRAM and NVRAM and the like, is supplied.

公开(公告)号：JP2000332132A

公开(公告)日：2000-11-30

申请号：JP2000116911

申请日：2000-04-18

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  JOHN JOSEF ELLIS-MONAHAN ,  ERIK RAY HEDBERG ,  HOOK TERENCE B ,  MANDELMAN JACK ALLAN ,  EDWARD JOSEF NOWACK ,  PRICER WILBUR DAVID ,  MIN HO TON ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0944

Abstract: PROBLEM TO BE SOLVED: To increase the threshold voltage of an FET element after switched from a floating state to a biased state by changing a bulk CMOS element to an element within a silicon substrate on an insulator. SOLUTION: A unit cell 1 includes an SOINMOS transistor 60, and its main body or an isolated SOI substrate region 62 is connected to main-body-device transistor switches 64 and 66. The switch 64 is connected to a reference signal 74. When operated by a control signal 80 applied to a gate 78, the switch 64 supplies the signal 74 to the main body 62 of the transistor 60. The main body 62 is connected to a reference signal 76 via a switch 66, and the switch 66 is operated by a control signal 84 supplied to a gate 80. In an active switching state, the threshold voltage level is low, and in a standby state, it is high.

公开(公告)号：JPH1117001A

公开(公告)日：1999-01-22

申请号：JP16022198

申请日：1998-06-09

Applicant: IBM

Inventor： MARK A JEISO ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an SOI(silicon on Insulator)/bulk hybrid semiconductor substrate. SOLUTION: A semiconductor device has SOI regions 120 and bulk regions 122. In single crystal semiconductor regions, conductive spacers 124 are provided to electrically connect the SOI regions to the ground, thereby overcoming the floating body effect. Insulative spacers 126 are formed on the conductive spacers 124 to electrically separate the SOI regions 120 from the bulk regions 122. In manufacturing process of these regions, a sacrificial polishing layer is deposited to the epitaxially grown single crystal bulk regions, and there is no need to selectively grow.

公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：MY117502A

公开(公告)日：2004-07-31

申请号：MYPI9802182

申请日：1998-05-15

Applicant: IBM

Inventor： JASO MARK A ,  MANDELMAN JACK A ,  TONTI WILLIAM R ,  WORDEMAN MATTHEW R

IPC: H01L27/01 ,  H01L21/00 ,  H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L31/0392

Abstract: A SEMICONDUCTOR DEVICE HAVING AREAS (100) THAT ARE SEMICONDUCTOR ON INSULATOR (SOI) AND AREAS (102) THAT ARE BULK, SINGLE CRYSTALLINE SEMICONDUCTIVE AREAS IS PROVIDED IN WHICH CONDUCTIVE SPACERS (105, 124) MAY BE FORMED TO ELECTRICALLY CONNECT THE SOI AREAS TO GROUND IN ORDER TO OVERCOME FLOATING BODY EFFECTS THAT CAN OCCUR WITH SOI. ADDITIONALLY, INSULATIVE SPACERS (107, 126) MAY BE FORMED ON THE SURFACE OF THE CONDUCTIVE SPACERS TO ELECTRICALLY ISOLATE THE SOI REGIONS (120) FROM THE BULK REGIONS (122). A NOVEL METHOD FOR MAKING BOTH OF THESE PRODUCTS IS PROVIDED IN WHICH THE EPITAXIALLY GROWN, SINGLE CRYSTALLINE BULK REGIONS NEED NOT BE SELECTIVELY GROWN, BECAUSE A SACRIFICIAL POLISHING LAYER IS DEPOSITED, IS ALSO PROVIDED.(FIG. 4)