公开(公告)号：DE60116774D1

公开(公告)日：2006-04-06

申请号：DE60116774

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN GUNTHER ,  BRINTZINGER AXEL

IPC: H01L23/525

Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses disposed on a same level in a fuse bank. A plurality of conductive lines are routed through the fuse bank in between the fuses. A terminal via window is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

公开(公告)号：DE102004050476B3

公开(公告)日：2006-04-06

申请号：DE102004050476

申请日：2004-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL ,  UHLENDORF INGO ,  RUCKMICH STEFAN ,  WALLIS DAVID

IPC: H01L23/50 ,  H01L21/48 ,  H05K7/20

Abstract: Masking layers (3) are applied and structured on both sides of the substrate wafer (1), to form a first contact location (6) on the first surface (11) and a second contact location (6) on the second surface (12). A protective layer is applied to the second surface, to protect the masking and contact on that side, during the following stages. A conductor structure (7) is deposited on the first surface (11), covering the first contact location. The protective layer on the second surface is removed, and the second conductor structure (7) is applied, to cover the second contact location on the second surface (12). In a further stage, a protective layer is applied to the first surface. Application of the masking layer on the first and second surfaces comprises evaporation, immersion coating and gas phase deposition. Structuring of the masking layer is carried out by lithographic- and etching processes. The first and/or second protective layer is applied using immersion coating, spray coating or rotation coating. The first and/or second protective layers are formed from plastic film, which is adhered or laminated to the respective surface. The substrate wafer is prepared from a silicon substrate.

公开(公告)号：DE102004028572A1

公开(公告)日：2006-01-12

申请号：DE102004028572

申请日：2004-06-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUHMANN CLAUDIA ,  GRUMM MATHIAS ,  BRINTZINGER AXEL ,  STROGIES JOERG ,  STADT MICHAEL ,  WALLIS DAVID

IPC: H01L23/50

Abstract: The device has a set of conducting paths connecting bond-pads with respective contact surfaces on a round end of a bump. The paths are arranged in two electrically connected sections (5, 8), where the section (5) runs in a plane starting from the bond-pads and the section (8) runs in another plane arranged over the former plane. The planes are electrically insulated form each other, where the lengths of the sections are same.

公开(公告)号：DE102004023897A1

公开(公告)日：2005-12-15

申请号：DE102004023897

申请日：2004-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO ,  WALLIS DAVID ,  RUCKMICH STEFAN

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

Abstract: The method involves galvanically depositing the copper cores of the tracks and contact pads in the mask openings of a resist mask made of positive resist, then removing their edges by a further lithographic process. The copper cores are then completely enclosed with a nickel-gold layer before the positive resist mask is removed. To expose the edges, the positive resist mask is completely removed and a second negative-resist mask is created so that the copper core of the track and contact pad including a completely surrounding edge region is kept free.

公开(公告)号：DE102004023752A1

公开(公告)日：2005-12-15

申请号：DE102004023752

申请日：2004-05-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  RUCKMICH STEFAN ,  TROVARELLI OCTAVIO

IPC: H01L21/3213 ,  H01L21/60 ,  H01L21/768

Abstract: The method involves applying a sacrificial layer (6) to the redistribution layer (4) for protecting the copper layer (3) below during subsequent etching processes. The resist mask is removed in a lift-off step, and the seed layer is then removed by etching.

公开(公告)号：DE102004031465A1

公开(公告)日：2005-09-08

申请号：DE102004031465

申请日：2004-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TROVARELLI OCTAVIO

IPC: H01L21/60 ,  H01L23/50 ,  H01L23/525

Abstract: An integrated circuit (1) has a bare fuse element (3) with a wiring area that can be cut through. A protective layer is applied over the wiring area of the fuse element. The surface of the integrated circuit is processed so as to form a re-wiring lead (7). The protective layer is removed so as to bare the wiring area of the fuse element. An independent claim is also included for an integrated circuit designed as a water level package with a re-wiring lead on a surface.

公开(公告)号：DE60011190T2

公开(公告)日：2005-06-30

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE102004025108A1

公开(公告)日：2005-03-10

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

公开(公告)号：DE10320561A1

公开(公告)日：2004-12-09

申请号：DE10320561

申请日：2003-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVLO ,  UHLENDORF INGO ,  WALLIS DAVID ,  BRINTZINGER AXEL

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/50

公开(公告)号：DE10318074A1

公开(公告)日：2004-12-09

申请号：DE10318074

申请日：2003-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TROVARELLI OCTAVIO ,  BRINTZINGER AXEL

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/485 ,  H01L21/60

Abstract: Process for improving the mechanical properties of BOC module arrangements comprises providing a wafer (1) or chips after their separation and before their assembly on a circuit board with a casting compound (5) so that the tips of the three-dimensional structures (2) protrude from them.