公开(公告)号：DE10032272C2

公开(公告)日：2002-08-29

申请号：DE10032272

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A bit line (BL) first driver (FD) (T1) has an FD current source (J3) and an FD n-channel field effect transistor (N6) with a channel width (wn). The FD current source and the FD field effect transistor connect in series between a BL source of voltage supply (V-SupplyBL) and the BL. A second driver (SD) (T2) for a word line (WL) has an SD current source (J0) that connects with an SD field effect transistor (N0) in series between a WL source of voltage supply (V-SupplyWL) and the WL.

公开(公告)号：DE10041378C1

公开(公告)日：2002-05-16

申请号：DE10041378

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  GOGL DIETMAR

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  H01L27/10

Abstract: A magnetoresistive RAM has many tunneling magnetoresistive memory cells in an array and connected to bitlines and wordlines at respective ends. The other cell ends from the bitlines are joined in at least two groups (1 to 4 or 5 to 8) to a switching transistor (TR1,2) whose gate connects to the corresponding wordline.

公开(公告)号：DE10051173A1

公开(公告)日：2002-04-25

申请号：DE10051173

申请日：2000-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/15

Abstract: Both ends of a selected word line (WL2) are set at a high voltage (V2) to keep the voltage drop on the selected word line as low as possible. A cell (Z22) is read out at an intersecting point between the selected word line and a bit line. Other word lines are set at another voltage level. An Independent claim is also included for a method for reducing the voltage drop along a word/bit line in an MRAM memory.

公开(公告)号：DE10041375A1

公开(公告)日：2002-03-21

申请号：DE10041375

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MUELLER GERHARD ,  GOGL DIETMAR ,  KANDOLF HELMUT

IPC: G11C11/15 ,  G11C17/16 ,  G11C29/00

Abstract: The arrangement includes several memory location fields (1-4) that are provided in a stack one above the other. Each memory location field has redundant memory locations which are provided in the boundary areas (5-8). The addresses of the memory locations to be replaced, are written in the memory cells provided in the boundary areas (9-12) of the memory location fields.

公开(公告)号：DE10034083C1

公开(公告)日：2002-03-14

申请号：DE10034083

申请日：2000-07-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10 ,  H01L23/528

Abstract: A memory matrix based on at least one cell array of column lines and row lines in which at least two column- or row-lines change their location relative to one another i.e. they cross-over one another. The memory matrix has cell arrays stacked in layers one above the other, and in which in each case the column- or row-lines of different layers lie mainly mutually adjacent, opposite one another.

公开(公告)号：DE10037976A1

公开(公告)日：2002-02-21

申请号：DE10037976

申请日：2000-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line

公开(公告)号：DE10032272A1

公开(公告)日：2002-01-24

申请号：DE10032272

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A bit line (BL) first driver (FD) (T1) has an FD current source (J3) and an FD n-channel field effect transistor (N6) with a channel width (wn). The FD current source and the FD field effect transistor connect in series between a BL source of voltage supply (V-SupplyBL) and the BL. A second driver (SD) (T2) for a word line (WL) has an SD current source (J0) that connects with an SD field effect transistor (N0) in series between a WL source of voltage supply (V-SupplyWL) and the WL.

公开(公告)号：DE60320301D1

公开(公告)日：2008-05-21

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE60305208T2

公开(公告)日：2006-12-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：DE50110560D1

公开(公告)日：2006-09-07

申请号：DE50110560

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: G11C11/00 ,  H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.