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    33.
    发明专利
    未知

    公开(公告)号：DE10016726A1

    公开(公告)日：2001-10-18

    申请号：DE10016726

    申请日：2000-04-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: The method involves the use of a pre-charge step that coincides with each drive phase of a short circuit transistor and during which the selection transistors are blocked. After the selection of memory cells the drive phases of the corresp. short circuit transistors of the selected cells are terminated by a negative potential on the corresp. word line of each short circuit transistor.

    35.
    发明专利
    未知

    公开(公告)号：DE10005618A1

    公开(公告)日：2001-08-30

    申请号：DE10005618

    申请日：2000-02-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LAMMERS STEFAN ,  MANYOKI ZOLTAN ,  HOENIGSCHMID HEINZ ,  BOEHM THOMAS

    IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

    Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

    39.
    发明专利
    未知

    公开(公告)号：DE60304209T2

    公开(公告)日：2006-12-14

    申请号：DE60304209

    申请日：2003-10-28

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

    IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

    Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

    40.
    发明专利
    未知

    公开(公告)号：DE69832566T2

    公开(公告)日：2006-08-10

    申请号：DE69832566

    申请日：1998-09-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

    IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L27/10

    Abstract: Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL1, LBL2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SAi). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i.e., the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL1) in a column is directly coupled via a switch (251) to an associated sense amplifier, whereas the other local bit lines in the column (LBL2-LBL4) are operatively coupled to the sense amplifier via the master bit line. The different local bit line lengths are preferably selected such that total bit line capacitance with respect to any of the memory cells is substantially equalized, thereby improving data retention time for the memory.

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