公开(公告)号：DE102004022884B4

公开(公告)日：2007-07-19

申请号：DE102004022884

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  WOERNER HOLGER ,  JEREBIC SIMON ,  BAUER MICHAEL

IPC: H01L23/50 ,  H01L21/48 ,  H01L21/52 ,  H01L21/60 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

公开(公告)号：DE102005007486A1

公开(公告)日：2006-08-31

申请号：DE102005007486

申请日：2005-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JEREBIC SIMON ,  BAUER MICHAEL ,  FUERGUT EDWARD ,  VILSMEIER HERMANN

IPC: H01L23/488 ,  H01L21/48 ,  H05K13/04

Abstract: A semiconductor component including a surface-mount housing and a method for producing the same are described herein. The semiconductor component includes lead pieces embedded into a plastic housing composition and arranged on an underside of the housing. External contact areas of the lead pieces are free of the plastic housing composition. A structured solderable coating is arranged on the external contact areas that have been kept free of the plastic housing composition, the coating includes a plurality of electrically conductive and mechanically elastic contact elements.

公开(公告)号：DE102004020497B8

公开(公告)日：2006-06-14

申请号：DE102004020497

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  WOERNER HOLGER ,  JEREBIC SIMON ,  BAUER MICHAEL

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/60 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

公开(公告)号：DE102004046227B3

公开(公告)日：2006-04-20

申请号：DE102004046227

申请日：2004-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  VILSMEIER HERMANN ,  JEREBIC SIMON ,  BAUER MICHAEL ,  BEMMERL THOMAS ,  THEUSS HORST ,  STUEMPFL CHRISTIAN

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/50

公开(公告)号：DE102004020497B3

公开(公告)日：2006-01-19

申请号：DE102004020497

申请日：2004-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  WOERNER HOLGER ,  JEREBIC SIMON ,  BAUER MICHAEL

IPC: H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

Abstract: A method of producing electrical through contacts (1) comprises forming a composite plate (2) having an upper semiconductor chip layer (3) with active surfaces and a lower layer of insulating plastic (4) filled with conductive particles (9). High voltage is applied through the sheet between point electrodes to form the contacts. An independent claim is also included for a semiconductor module produced as above.

公开(公告)号：DE10332017A1

公开(公告)日：2005-03-03

申请号：DE10332017

申请日：2003-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZEILER THOMAS ,  JEREBIC SIMON ,  ERNST GEORG ,  GROENINGER HORST

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495

Abstract: An electronic component includes a semiconductor chip and a leadframe. The leadframe includes a metal coating pattern on its underside to facilitate the application of solder to the electronic component. The metal coating pattern includes wetting regions that are wettable with solder material and anti-wetting regions that are unwettable with solder material, and the electronic component includes solder deposits formed on the wetting regions on the underside of the component.

公开(公告)号：DE102007050608A1

公开(公告)日：2009-04-30

申请号：DE102007050608

申请日：2007-10-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  WOERNER HOLGER ,  JEREBIC SIMON

IPC: H01L23/057 ,  H01L21/60 ,  H01L23/48

公开(公告)号：DE102005023949A1

公开(公告)日：2006-11-30

申请号：DE102005023949

申请日：2005-05-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  VILSMEIER HERMANN ,  JEREBIC SIMON ,  BAUER MICHAEL ,  BEMMERL THOMAS

IPC: H01L23/04 ,  H01L21/60 ,  H01L23/50

Abstract: The invention relates to a panel and a semiconductor device including a composite plate with semiconductor chips and a plastic packaging compound, and to processes for producing them. For this purpose, the panel having a composite plate has semiconductor chips arranged in rows and columns on a top side of a wiring substrate. The wiring substrate is covered by a plastic packaging compound in a plurality of semiconductor device positions, the rear sides of the semiconductor chips being fixed on the wiring substrate. A plastic packaging compound in the region of the boundary surfaces with the semiconductor chips has a coefficient of thermal expansion which is matched to that of silicon, while the remaining plastic packaging compound has a coefficient of thermal expansion which is matched to that of the wiring substrate and is therefore correspondingly higher.

公开(公告)号：DE102004059599B3

公开(公告)日：2006-08-17

申请号：DE102004059599

申请日：2004-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JEREBIC SIMON ,  STROBEL PETER

IPC: H01L21/58 ,  H01L21/78 ,  H01L21/673

Abstract: The invention relates to a method for applying an adhesive layer to ground-thin or thinned semiconductor chips of a semiconductor wafer. In this case, the adhesive layer, with the aid of an adhesive film which is entirely composed of precurable adhesive, is introduced relatively early into a method for the thinning by grinding, separation and singulation of a semiconductor wafer to form thinned semiconductor chips, and is finally used further in the semiconductor device into which the thinned semiconductor chip is to be incorporated.

公开(公告)号：DE102004025279A1

公开(公告)日：2005-12-15

申请号：DE102004025279

申请日：2004-05-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FUERGUT EDWARD ,  VILSMEIER HERMANN ,  JEREBIC SIMON ,  BAUER MICHAEL ,  BEMMERL THOMAS

IPC: B23K3/06 ,  H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H05K3/22 ,  H05K3/34 ,  H05K13/00

Abstract: A support with solder ball elements for loading substrates with ball contacts is disclosed. One embodiment provides a system for loading substrates with ball contacts and a method for loading substrates with ball contacts. The support has a layer of adhesive applied on one side, the layer of adhesive losing its adhesive force to the greatest extent when irradiated. The support has solder ball elements, which are arranged closely packed in rows and columns on the layer of adhesive in a prescribed pitch for a semiconductor chip or a semiconductor component.