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    DISPOSITIF A MEMOIRE INTEGREE ET PROCEDE
    36.
    发明专利
    DISPOSITIF A MEMOIRE INTEGREE ET PROCEDE 未知

    公开(公告)号：FR2879800A1

    公开(公告)日：2006-06-23

    申请号：FR0507831

    申请日：2005-07-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUFER KLAUS ,  SHUM DANNY PAK CHUM

    IPC: G11C11/40 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/861

    Abstract: Un dispositif à mémoire utilisant des transistors à effet de champ à effet tunnel (TFET) et des lignes de bits enterrées, est présenté. Le dispositif à mémoire comprend une matrice contenant des rangées et des colonnes de cellules de mémoire. Chaque cellule de mémoire contient au moins un transistor de cellule qui à son tour, contient des premières régions dopées et des deuxièmes régions dopées, l'une d'entre elles étant une source et l'autre un drain. Le dispositif à mémoire comprend des lignes WL0 à WL4 de mots dont chacune est reliée à des cellules de mémoire d'une rangée, et des lignes de bits WO à WZ dont chacune est reliée à des cellules de mémoire d'une colonne. Les premières régions dopées sont d'un type de dopage différent de celui des deuxièmes régions dopées.

    38.
    发明专利
    未知

    公开(公告)号：DE102004015899A1

    公开(公告)日：2005-10-20

    申请号：DE102004015899

    申请日：2004-03-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SHUM DANNY ,  KAKOSCHKE RONALD

    IPC: H01L27/24 ,  H01L45/00 ,  H01L21/82

    Abstract: The invention relates to a method for producing a PCM memory element and to a corresponding PCM element. The method of production comprises the following steps: providing a first and a second line device (Ma, Mb) underneath an insulating layer ( 10 ); providing a hole ( 5 a, 5 b) in the insulation layer ( 10 ), which partially exposes the first and the second line device (Ma, Mb); providing, as the respective lower electrode, a respective strip-shaped resistor element ( 20; 20'; 20'' ) on the wall of the hole (5a, 5b), which electrically contacts the exposed first or second line device (Ma, Mb): providing a filling ( 30 ) from an insulating material in the hole ( 5 a, 5 b) between the strip-shaped resistor elements ( 20; 20'; 20'' ); providing a layer ( 35 ) produced from a PCM material in the hole ( 5 a, 5 b), which electrically contacts the strip-shaped resistor elements ( 20; 20'; 20'' ) on their upper faces; providing a conducting layer ( 40 ) above the hole ( 5 a, 5 b) and the surrounding surface of the insulating layer ( 10 ): forming a sublithographic masking strip ( 50 ) on the conducting layer ( 40 ) above the hole ( 5 a, 5 b) and the surrounding surface of the insulating layer ( 210 ) at an angle to the direction of the first and second line device (Ma, Mb): forming segments of the mask strip ( 50 ); structuring the conducting layer ( 40 ) and the layer ( 35 ) produced from the PCM material while using the segments for forming the respective upper electrode from the conducting layer ( 40 ) and a PCM area of the layer ( 35 ) produced from PCM material lying between the upper and the lower electrode: removing the mask strip ( 50 ); and electrically connecting the upper electrode to an additional line device ( 80 ).

    39.
    发明专利
    未知

    公开(公告)号：DE10117037A1

    公开(公告)日：2002-10-17

    申请号：DE10117037

    申请日：2001-04-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAKOSCHKE RONALD ,  WILLER JOSEF

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/12

    Abstract: A memory cell array comprising a plurality of memory transistors (1, 2, 3, 4), arranged in a two-dimensional array, each memory transistor having two source/drain areas(14a, 14b, 14c, 14d) which are arranged in a first direction of the memory cell area with a channel substrate area (19) therebetween, in addition to a gate structure (20) arranged above the channel substrate area (18). The source/drain areas(14a, 14b, 14c, 14d) and the channel substrate areas (18) are formed in a substrate (16) arranged on an insulating layer (12). The channel substrate areas (18) of adjacent memory transistors in the same direction are separated from each other by respective source/drain areas extending as far as the insulating layer (12). The source/drain areas (14a, 14b, 14c, 14d) and the channel substrate areas (18) of memory transistors adjacent in a second direction of the storage cell array are insulated with respect to each other by trenches (30) formed in the substrate (16) filled with an insulating material and extending as far as the insulating layer (12).

    Memory cell arrays and method for the production thereof
    40.
    发明专利
    Memory cell arrays and method for the production thereof 未知

    公开(公告)号：AU2002338242A1

    公开(公告)日：2002-10-15

    申请号：AU2002338242

    申请日：2002-02-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WILLER JOSEF ,  KAKOSCHKE RONALD

    IPC: H01L27/10 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

    Abstract: A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, said metallizations being insulated from the gate region layer by the insulating spacer layers.

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