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公开(公告)号：DE10037976A1
公开(公告)日：2002-02-21
申请号：DE10037976
申请日：2000-08-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GOGL DIETMAR , KANDOLF HELMUT , LAMMERS STEFAN
IPC: G11C11/14 , G11C5/06 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line
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公开(公告)号：DE10034928A1
公开(公告)日：2002-02-07
申请号：DE10034928
申请日：2000-07-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FISCHER HELMUT , KANDOLF HELMUT , LAMMERS STEFAN
Abstract: The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.
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公开(公告)号：DE10032256A1
公开(公告)日：2002-01-24
申请号：DE10032256
申请日：2000-07-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAMMERS STEFAN , MANYOKI ZOLTAN
Abstract: A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.
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公开(公告)号：DE10011180A1
公开(公告)日：2001-09-27
申请号：DE10011180
申请日：2000-03-08
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BOEHM THOMAS , MANYOKI ZOLTAN , LAMMERS STEFAN , KANDOLF HELMUT
Abstract: The circuit includes an information memory with an addressing device with a decoder and an input circuit. The number of address terminal contacts (11,12) is equal to a sum Z+S, where Z is the number of bits required by M elements, and S is the number of bits required by N elements. The numbers P and Q are selected so that for addressing P elements K less than or equal to (Z-2) bits are required and for addressing Q elements L less than or equal to (S-2) bits are required. The input circuit (11-36) has an additional control bit contact (13) and a switchover device (31-34) which receives a control bit to set a first operating mode or a second, third or fourth operating mode accordingly.
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公开(公告)号：DE50110560D1
公开(公告)日：2006-09-07
申请号：DE50110560
申请日：2001-10-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FREITAG MARTIN , HOENIGSCHMID HEINZ , GOGL DIETMAR , LAMMERS STEFAN
IPC: G11C11/00 , H01L27/105 , G11C11/16 , H01L21/8246 , H01L27/22 , H01L43/08
Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.
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Patent Agency Ranking
公开(公告)号：DE102006001117A1
公开(公告)日：2006-08-17
申请号：DE102006001117
申请日：2006-01-09
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor： DEBROSSE JOHN , GOGL DIETMAR , LAMMERS STEFAN , VIEHMANN HANS-HEINRICH
Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
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公开(公告)号：DE10010456B4
公开(公告)日：2005-10-27
申请号：DE10010456
申请日：2000-03-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： KANDOLF HELMUT , ROEHR THOMAS , HOENIGSCHMID HEINZ , LAMMERS STEFAN
IPC: G11C11/22 , G11C5/14 , G11C7/18 , G11C8/14 , G11C11/4097 , G11C16/28 , H01L27/115
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公开(公告)号：DE10055936C2
公开(公告)日：2003-08-28
申请号：DE10055936
申请日：2000-11-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FREITAG MARTIN , GOGL DIETMAR , LAMMERS STEFAN , HOENIGSCHMID HEINZ
IPC: H01L27/105 , G11C11/16 , H01L21/8246 , H01L27/22 , H01L43/08 , G11C11/14 , G11C11/15
Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.
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公开(公告)号：DE10032256C2
公开(公告)日：2003-06-05
申请号：DE10032256
申请日：2000-07-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAMMERS STEFAN , MANYOKI ZOLTAN
Abstract: A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.
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公开(公告)号：DE10037976C2
公开(公告)日：2003-01-30
申请号：DE10037976
申请日：2000-08-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GOGL DIETMAR , KANDOLF HELMUT , LAMMERS STEFAN
IPC: G11C11/14 , G11C5/06 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line
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