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    31.
    发明专利
    未知

    公开(公告)号：DE10034255C2

    公开(公告)日：2002-05-16

    申请号：DE10034255

    申请日：2000-07-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JOHNSON BRET ,  PLAETTNER ECKHARD ,  SCHNEIDER HELMUT

    IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/407

    Abstract: A circuit arrangement for reading and writing binary information to a storage location array having a matrix-type arrangement of rows and columns, has a switching device (T9) which interrupts the current supply, after excitation of a any word-line, to the latch-flip-flops (T1-T4) in the write-read circuits (LV2) under control of a column-selection signal (SAS), at a time-point not before the relevant latch-flip-flop has assumed a condition indicating the information content of the accessed memory location, and which at the latest occurs in the active interval of the relevant column-selection signal.

    34.
    发明专利
    未知

    公开(公告)号：DE19948570C2

    公开(公告)日：2001-07-26

    申请号：DE19948570

    申请日：1999-10-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

    IPC: G03F1/00 ,  H01L21/768 ,  H01L23/522

    Abstract: A configuration for connecting conductor tracks includes a first conductor track fabricated with a first phase mask having a first phase and a second conductor track fabricated with a second phase mask having a second phase opposite to the first phase. The first and second conductor tracks define a given metallization plane and are disposed on this given metallization plane. The first conductor track adjoins the second conductor track in a junction region such that a discontinuity is provided between the first conductor track and the second conductor track. A connecting contact is disposed above or below the given metallization plane and connects the conductor tracks in the junction region. Moving the connection above or below the metallization plane avoids phase conflicts in the junction region. A method of electrically connecting conductor tracks is also provided.

    35.
    发明专利
    未知

    公开(公告)号：DE10222892B4

    公开(公告)日：2008-04-24

    申请号：DE10222892

    申请日：2002-05-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CHRISSOSTOMIDIS IOANNIS ,  GRAF VON KEYSERLINGK ALBERT ,  SCHNEIDER HELMUT

    IPC: G11C7/22 ,  G11C7/10

    Abstract: An integrated memory has a respective terminal for a clock signal and a data clock signal and also a data terminal. For a write operation, the memory accepts a write command on account of the clock signal and, in a manner time-delayed with respect thereto, a plurality of data at the data terminal on account of the data clock signal. An access controller serves for controlling an access to a memory cell array of the memory for the parallel writing of the accepted data to selected memory cells. The access to the memory cell array is triggered by the access controller by a phase-shifted clock signal before the clock signal has a next rising edge after the acceptance of the data. It is thus possible to increase the effective writing time from the application of the write command to the closing of a memory bank by a precharge command.

    36.
    发明专利
    未知

    公开(公告)号：DE59913873D1

    公开(公告)日：2006-11-09

    申请号：DE59913873

    申请日：1999-05-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  LE THOAI-THAI

    IPC: G11C17/18 ,  G11C29/04 ,  G11C17/16

    Abstract: The circuit reads information from a fuse (10), and stores it in a latch (1) in response to a first and a second control signal which are temporary displaced with respect to each other. Both, the first control signal (FINIT) and the second control signal (FSET) are won from a single, global initialisation signal, by device of a delay element. The delay element consists preferably of transistors (14,15,17), whereby further invertors (12,13) are provided for the delay. The fuse is preferably arranged between the source-drain paths of two MOSFETs (5,9) of the same conductivity.

    37.
    发明专利
    未知

    公开(公告)号：DE10134178B4

    公开(公告)日：2006-09-21

    申请号：DE10134178

    申请日：2001-07-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT

    IPC: H01L27/105 ,  H01L21/761

    Abstract: The invention relates to a semiconductor memory (1) having a plurality of memory-cell arrays (2), a plurality of sense-amplifier areas (3) and a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multiple sense-amplifier areas (3) and multiple driver areas (4) containing at least one first well (9) of the first conductivity type and/or at least one second well (10) of a second conductivity type, and each first well (9) of the driver areas (4) being isolated from the semiconductor substrate (7) by a buried horizontal layer (8) of the second conductivity type.In order to ensure less space is required, the semiconductor memory according to the invention exhibits the features that the buried horizontal layer (8) extends continuously beneath at least all the memory-cell arrays (2) and the multiple driver areas (4) of the semiconductor memory (1), and that a separation (6) is provided between the second well (10) and the buried horizontal layer (8) so that the second well (10) is electrically isolated from the buried horizontal layer (8). Semiconductor memory having a plurality of memory-cell arrays

    39.
    发明专利
    未知

    公开(公告)号：DE59912177D1

    公开(公告)日：2005-07-21

    申请号：DE59912177

    申请日：1999-08-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHNEIDER HELMUT ,  WAGNER MICHAEL

    IPC: G11C7/12 ,  H01L21/8242 ,  H01L27/108

    Abstract: A combined precharging and homogenizing circuit for a semiconductor memory configuration made up of a memory cell array having a multiplicity of bit line pairs. The combined precharging and homogenizing circuit containing a first and a second field-effect precharging transistor and a homogenizing transistor connected in series between the two precharging transistors. Gates of the two precharging transistors and of the homogenizing transistor are connected together to form a common gate. Sources of the precharging transistors are connected together to form a common source. A drain of the first precharging transistor and a drain of the homogenizing transistor are connected together to form a common drain and the source of the homogenizing transistor and the drain of the second precharging transistor are connected together to form a common source/drain. In the combined precharging and homogenizing circuit, the invention provides that the common gate is angled and is configured rotated through about 45 DEG in relation to a longitudinal direction of the bit lines. In addition, the common drain and the common source/drain are drawn forward beyond the common gate defining protruding regions, and that bit line contacts are accommodated in the protruding regions.

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