公开(公告)号：DE59712601D1

公开(公告)日：2006-05-11

申请号：DE59712601

申请日：1997-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  WENDT HERMANN ,  WILLER JOSEF ,  LEHMANN VOLKER ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  KRAUTSCHNEIDER WOLFGANG ,  HOFMANN FRANZ

IPC: H01L21/8247 ,  H01L29/792 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788

Abstract: The invention concerns a non-volatile storage cell having a MOS transistor which, as gate dielectric, comprises a triple dielectric layer (5) consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The MOS transistor gate electrode comprises p -doped silicon such that, when a negative voltage is applied to the gate electrode, holes tunnel predominantly from the channel area (4) through the first silicon oxide layer (51) and into the silicon nitride layer (52).

公开(公告)号：DE50205382D1

公开(公告)日：2006-01-26

申请号：DE50205382

申请日：2002-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/082 ,  H01L27/12

公开(公告)号：DE10324081B4

公开(公告)日：2005-11-17

申请号：DE10324081

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/30 ,  G11C11/21 ,  G11C19/00 ,  H01L21/762

公开(公告)号：DE10317098A1

公开(公告)日：2004-07-22

申请号：DE10317098

申请日：2003-04-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MEISTER THOMAS ,  BOECK JOSEF ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737

Abstract: Production of bipolar transistor involves formation of semiconductor substrate with n type collector region, provision of single crystal p type base region and basic p type junction region over the basic n,p region, provision of insulation region over base p type junction region, formation of window (F) in the insulation region, provision of side wall spacers in the window, and differential separation and structuring of emitter layer.

公开(公告)号：DE59906526D1

公开(公告)日：2003-09-11

申请号：DE59906526

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN ,  STENGL REINHARD ,  LANGE GERRIT ,  OTTOW STEFAN

IPC: C25F3/12 ,  C25F3/02 ,  H01P1/20

Abstract: A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the pores. The entire surface of the substrate is covered with a mask layer that is structured photolithographically on the rear of the substrate. The bottoms of the pores in the second region are etched clear, preferably using KOH.

公开(公告)号：DE10151132A1

公开(公告)日：2003-05-08

申请号：DE10151132

申请日：2001-10-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: The invention concerns a semiconductor structure comprising a substrate (10), an insulating layer (14) arranged on one surface of the substrate (10), a layer (18) for components arranged on one surface (16) of the insulating layer (14) opposite the substrate (10), a semiconductor component (30a, 30b) arranged in the layer (18) for components and zone designed for capacitively uncoupling said semiconductor component (30a, 30b) relative to the substrate (10), said zone being formed by a space charge zone (96) formed in a region of the substrate (10) adjacent to the insulating layer (14).

公开(公告)号：DE19958062C2

公开(公告)日：2002-06-06

申请号：DE19958062

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  BOECK JOSEF ,  KLEIN WOLFGANG

IPC: H01L21/331 ,  H01L29/732 ,  H01L21/8222 ,  H01L27/082

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.