公开(公告)号：DE10312202B4

公开(公告)日：2005-06-02

申请号：DE10312202

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  WEGE STEFAN ,  VOGT MIRKO ,  MOLL HANS-PETER

IPC: H01L21/32 ,  B81C1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/334 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

公开(公告)号：DE10314274B3

公开(公告)日：2004-09-16

申请号：DE10314274

申请日：2003-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  GENZ OLIVER ,  STAVREV MOMTCHIL ,  VOGT MIRKO

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/283

Abstract: Production of a first contact perforated surface in a storage device having storage cells comprises preparing a semiconductor substrate (1) with an arrangement of gate electrode strips (2) on the semiconductor surface, forming an insulating layer (3) on the semiconductor surface, forming a sacrificial layer on the insulating layer, forming material plugs on the sacrificial layer, producing a glass-like layer (8) exposing sacrificial layer blocks over contact openings between the gate electrode strips, etching the sacrificial material, removing the exposed insulating layer over the contact openings, and filling the contact opening regions with a conducting material (9). The sacrificial layer is formed by depositing a first sacrificial layer on the insulating layer, planarizing and depositing a second sacrificial layer.

公开(公告)号：DE10229463A1

公开(公告)日：2004-01-15

申请号：DE10229463

申请日：2002-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEDEL STEPHAN ,  STEIN VON KAMIENSKI ELARD ,  POLEI VERONIKA ,  VOGT MIRKO

IPC: H01L21/8246 ,  H01L23/552 ,  H01L27/115 ,  H01L23/52 ,  H01L21/8247 ,  H01L21/768

Abstract: A semiconductor configuration has an active region, a metalization layer having at least one metal plane, and connecting lines between the active region and the metalization layer. The least one metal plane is embedded in an intermetal dielectric. A UV protection plane is integrated with the metalization layer. A method for fabricating such a semiconductor configuration is also provided.

公开(公告)号：DE10153310A1

公开(公告)日：2003-05-22

申请号：DE10153310

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KIRCHHOFF MARKUS ,  WEGE STEPHAN ,  STEGEMANN MAIK ,  VOGT MIRKO

IPC: G03F7/36 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/314 ,  G03F7/40

Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

公开(公告)号：DE10138909A1

公开(公告)日：2003-02-27

申请号：DE10138909

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOGT MIRKO

IPC: C23C16/34 ,  G03F7/09 ,  H01L21/311 ,  H01L21/318 ,  C23F4/00 ,  H01L21/312

Abstract: Production of a silicon-containing layer (10') to be structured using a photomask comprises applying the silicon-containing layer on a substrate (1) using a chemical vapour deposition (CVD) process and using the excess silicon to reduce reflections from the light used for exposing the photomask. Preferably the excess silicon is adjusted so that the extinction coefficient of the layer is at least 0.05 at a wavelength of 345-365 nm. The layer is a silicon nitride layer or a silicon oxide layer. SiH4 and NH3 are used as carrier gases in the CVD process.

公开(公告)号：DE10053915C2

公开(公告)日：2002-11-14

申请号：DE10053915

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHR MATTHIAS UWE ,  TEWS RENE ,  VOGT MIRKO

IPC: H01L21/3213 ,  H01L21/768