公开(公告)号：WO2004025714A3

公开(公告)日：2004-05-13

申请号：PCT/EP0309551

申请日：2003-08-28

Applicant: INFINEON TECHNOLOGIES AG ,  GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

Inventor： GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L21/76811 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

Abstract: The invention relates to a method for production of a semiconductor structure, comprising the steps: preparation of a semiconductor substrate (1), generation of a lower first, a middle second and an upper third masking layer (5, 7, 9) on a surface of the semiconductor substrate (1), formation of at least one first window (11, 11a-h) in the upper third masking layer (9), structuring the middle second masking layer (7) using the first window (11, 11a-h) in the upper third masking layer (9) for the transfer of the first window (11, 11a-h), structuring the lower first masking layer (5) using the first window (11, 11a-h) in the middle second masking layer (7) for the transfer of the first window (11, 11a-h), enlarging the first window (11, 11a-h) in the upper third masking layer (9) to form a second window (13, 13a-b) in a maskless process step, restructuring the middle second masking layer (7) using the second window (13, 13a-b) in the upper third masking layer (9) for the transfer of the second window (13, 13a-b), structuring the semiconductor substrate (1), using the structured lower third masking layer (5), restructuring the lower first masking layer (5) using the second window (13, 13a-b) in the middle second masking layer (7) and restructuring the semiconductor substrate (1) using the restructured lower third masking layer (5).

Abstract translation: 本发明提供了一种半导体结构制造方法，包括以下步骤：提供半导体衬底（1）; 在所述半导体衬底（1）的表面上提供下第一掩膜层，中间第二掩膜层和上第三掩膜层（5,7,9）; 在所述上部第三掩模层（9）中形成至少第一窗口（11,11a-h）; 使用上部第三掩模层（9）中的第一窗口（11,11a-h）图案化中间第二掩模层（7）以传递第一窗口（11,11a-h）; 使用中间第二掩模层（7）中的第一窗口（11,11a-h）构造下部第一掩模层（5）以传送第一窗口（11,11a-h）; 扩大上部第三掩模层（9）中的第一窗口（11,11a-h）以在无掩模工艺步骤中形成第二窗口（13,13a-b）; 使用上部第三掩模层（9）中的第二窗口（13,13a-b）重构中央第二掩模层（7）以传送第二窗口（13,13a-b）; 使用图案化的下第三掩模层（5）图案化半导体衬底（1）; 使用中间第二掩模层（7）中的第二窗口（13,13a-b）重构下部第一掩模层（5）; 以及使用重构的下第三掩模层（5）重构半导体衬底（1）。

公开(公告)号：DE102005015502B4

公开(公告)日：2007-03-08

申请号：DE102005015502

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUDWIG FRANK ,  STAVREV MOMTCHIL ,  SCIRE ALESSIA ,  WILSON KIMBERLY ,  PEARS KEVIN

IPC: H01L21/3065 ,  H01L21/764 ,  H01L21/8242

公开(公告)号：DE102004020834A1

公开(公告)日：2005-11-17

申请号：DE102004020834

申请日：2004-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  WEGE STEPHAN ,  KLIPP ANDREAS ,  HAUPT MORITZ ,  SPERLICH HANS-PETER

IPC: H01L21/3065 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate ( 1 ); providing and patterning a silicon nitride layer ( 3 ) on the semiconductor substrate ( 1 ) as topmost layer of a trench etching mask; forming a trench ( 5 ) in a first etching step by means of the trench etching mask; conformally depositing a liner layer ( 10 ) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench ( 5 ); carrying out a V plasma etching step for forming a V profile of the line layer ( 10 ) in the trench ( 5 ); wherein the liner layer ( 10 ) is pulled back to below the top side of the silicon nitride layer ( 3 ); an etching gas mixture comprises C 5 F 8 , O 2 and an inert gas is used in the V plasma etching step; the ratio (V) of C 5 F 8 /O 2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

公开(公告)号：DE50312208D1

公开(公告)日：2010-01-21

申请号：DE50312208

申请日：2003-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GENZ OLIVER ,  KIRCHHOFF MARKUS ,  MACHILL STEFAN ,  REB ALEXANDER ,  SCHMIDT BARBARA ,  STAVREV MOMTCHIL ,  STEGEMANN MAIK ,  WEGE STEPHAN

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244

Abstract: Production of a semiconductor structure comprises preparing a semiconductor substrate, providing a lower first, a middle second and an upper third mask layer (5,7,9) on a surface of the substrate, forming a first window (11) in the third mask layer, structuring the second mask layer using the window, structuring the first mask layer using the window, enlarging the window in the third mask layer to form a second window (13), restructuring the second mask layer using the second window, structuring the substrate using the structured third mask layer, restructuring the first mask layer using the second window, and restructuring the substrate using the third mask layer.

公开(公告)号：DE10338665A1

公开(公告)日：2005-03-31

申请号：DE10338665

申请日：2003-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULER FRANZ ,  STAVREV MOMTCHIL ,  LUDWIG CHRISTOPH ,  HATZOPOULOS NIKOLAOS

IPC: H01L21/762 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

Abstract: Production of insulating regions in semiconductor memories comprises forming a hard mask (4) with openings (7) in the region of a stronger electrical insulation and in the region of a weaker electrical insulation on a substrate (1), closing the openings in the region of weaker electrical insulation using a filler (10), etching trenches in the substrate using the mask, removing the filler, etching again, removing the mask and filling the trenches with a dielectric.

公开(公告)号：DE10312202A1

公开(公告)日：2004-10-07

申请号：DE10312202

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  WEGE STEFAN ,  VOGT MIRKO ,  MOLL HANS-PETER

IPC: H01L21/32 ,  B81C1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/334 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

公开(公告)号：DE102020122871A1

公开(公告)日：2022-03-03

申请号：DE102020122871

申请日：2020-09-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  MEINHOLD DIRK

IPC: H01L25/16 ,  B81B7/00 ,  B81B7/02 ,  G01B17/00 ,  G01D11/24 ,  G01L9/12 ,  G01P15/00 ,  H01L23/10 ,  H01L23/482 ,  H01L23/49 ,  H01L29/84 ,  H01L43/06 ,  H04R1/00

Abstract: Vorgeschlagen wird ein Halbleiter-Die (100), wobei der Halbleiter-Die (100) einen mikroelektronischen Abschnitt (101) und einen Sensorabschnitt (103) aufweist. Der mikroelektronische Abschnitt (101) weist einen integrierten Schaltkreis (102) auf. Der Sensorabschnitt (103) grenzt an einen Rand (104) des Halbleiter-Dies (100). Ebenso wird ein Sensor vorgeschlagen, welcher einen solchen Halbleiter-Die (100) umfasst.

公开(公告)号：DE102005015502A1

公开(公告)日：2006-11-02

申请号：DE102005015502

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUDWIG FRANK ,  STAVREV MOMTCHIL ,  SCIRE ALESSIA ,  WILSON KIMBERLY ,  PEARS KEVIN

IPC: H01L21/3065 ,  H01L21/764 ,  H01L21/8242

Abstract: The method involves opening a mask on an upper surface of a silicon substrate. Uncovered surface sections are exposed to etching gas having etching gas components etching silicon, passive gas components passivating the silicon and the etching gas components etching a passivation section. The components are aligned one over other such that etching depth at two different sized upper surface sections has same/approximately same size. The etching gas component etching the silicon is a gas mixture containing silicon chloride and silicon fluoride. The etching gas component etching a passivation section is a gas mixture containing methane, gas mixture containing tri fluoro methane, gas mixture containing nitrogen fluoride and gas mixture containing sulphur hexa fluoride.

公开(公告)号：DE10312202B4

公开(公告)日：2005-06-02

申请号：DE10312202

申请日：2003-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAVREV MOMTCHIL ,  WEGE STEFAN ,  VOGT MIRKO ,  MOLL HANS-PETER

IPC: H01L21/32 ,  B81C1/00 ,  H01L21/302 ,  H01L21/308 ,  H01L21/334 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

公开(公告)号：DE10314274B3

公开(公告)日：2004-09-16

申请号：DE10314274

申请日：2003-03-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAF WERNER ,  HEINECK LARS ,  GENZ OLIVER ,  STAVREV MOMTCHIL ,  VOGT MIRKO

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/283

Abstract: Production of a first contact perforated surface in a storage device having storage cells comprises preparing a semiconductor substrate (1) with an arrangement of gate electrode strips (2) on the semiconductor surface, forming an insulating layer (3) on the semiconductor surface, forming a sacrificial layer on the insulating layer, forming material plugs on the sacrificial layer, producing a glass-like layer (8) exposing sacrificial layer blocks over contact openings between the gate electrode strips, etching the sacrificial material, removing the exposed insulating layer over the contact openings, and filling the contact opening regions with a conducting material (9). The sacrificial layer is formed by depositing a first sacrificial layer on the insulating layer, planarizing and depositing a second sacrificial layer.