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公开(公告)号:FR2839388A1
公开(公告)日:2003-11-07
申请号:FR0205539
申请日:2002-05-03
Applicant: ST MICROELECTRONICS SA
Inventor: MONFRAY STEPHANE , DUTARTRE DIDIER , BOEUF FREDERIC
IPC: H01S5/34 , H01L33/00 , H01L21/336 , H04L9/00
Abstract: An integrated circuit, incorporating a semiconductor device forming the source of a single photon, comprises on a silicon substrate (SB): (a) a MOS transistor (TR) having a grid in the shape of a mushroom, capable of delivering on its drain, in a controlled manner, a single electron in response to a control voltage applied on its grid; (b) at least one compatible silicon quantum box (BQ), electrically coupled to the drain region (D) of the transistor, and capable of emitting a single photon on the reception of a single electron emitted by the transistor. Independent claims are also included for: (a) a cryptographic device incorporating this integrated circuit; (b) a method for the fabrication of this integrated circuit; (c) a method for the emission of a single photon using this integrated circuit.
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公开(公告)号:FR2818012B1
公开(公告)日:2003-02-21
申请号:FR0016174
申请日:2000-12-12
Applicant: ST MICROELECTRONICS SA
Inventor: SKOTNICKI THOMAS , MONFRAY STEPHANE , HAOND MICHEL
IPC: H01L29/06 , H01L29/10 , H01L29/80 , H01L27/105
Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
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公开(公告)号:FR3009907A1
公开(公告)日:2015-02-27
申请号:FR1358072
申请日:2013-08-20
Inventor: MONFRAY STEPHANE , MAITRE CHRISTOPHE , KOKSHAGINA OLGA , SKOTNICKI THOMAS , SOUPREMANIEN ULRICH
Abstract: L'invention concerne un dispositif (400) de conversion d'énergie, comprenant une enceinte (430) contenant des gouttes d'un liquide (427) et un transducteur capacitif à électret (417, 419, 421) couplé à cette enceinte.
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公开(公告)号:FR2982424B1
公开(公告)日:2014-01-10
申请号:FR1160209
申请日:2011-11-09
Applicant: COMMISSARIAT ENERGIE ATOMIQUE , ST MICROELECTRONICS SA
Inventor: MONFRAY STEPHANE , SAVELLI GUILLAUME , SKOTNICKI THOMAS , CORONEL PHILIPPE , GAILLARD FREDERIC
IPC: H01L37/00
Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.
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公开(公告)号:FR2857952A1
公开(公告)日:2005-01-28
申请号:FR0309106
申请日:2003-07-25
Applicant: ST MICROELECTRONICS SA
Inventor: MONFRAY STEPHANE , ANCEY PASCAL , SKOTNICKI THOMAS , SEGUENI KARIM
Abstract: The resonator has a monocrystalline silicon substrate provided with an active zone surrounded by a shallow trench isolation region (STI). A vibrating beam is anchored on the region by one of free ends (14, 16) and comprises a monocrystalline silicon median part (12). A control electrode (E) is placed above the beam and is supported on the active zone. The median part is separated from the active zone and the electrode. An independent claim is also included for a method of manufacturing an electromechanical resonator.
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公开(公告)号:FR2819341B1
公开(公告)日:2003-06-27
申请号:FR0100295
申请日:2001-01-11
Applicant: ST MICROELECTRONICS SA
Inventor: SKOTNICKI THOMAS , MONFRAY STEPHANE , MALLARDEAU CATHERINE
IPC: H01L21/8242 , H01L27/108
Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.
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