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    31.
    发明专利
    未知

    公开(公告)号：DE69324694T2

    公开(公告)日：1999-10-07

    申请号：DE69324694

    申请日：1993-12-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00 ,  G06F11/20

    Abstract: A plurality of identical circuit blocks (PG0-PG15) is supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix; each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (C00-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated; a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) has the respective carry-in input (C10) connected to a reference voltage (GND); each of said circuit blocks (PG0-PG15) is also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) if the carry-out (C00-C014) signal supplying the respective carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) can be simultaneously selected.

    33.
    发明专利
    未知

    公开(公告)号：DE69411532T2

    公开(公告)日：1999-03-04

    申请号：DE69411532

    申请日：1994-02-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C29/00 ,  G11C29/04 ,  G06F11/20

    Abstract: A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.

    35.
    发明专利
    未知

    公开(公告)号：DE69424523T2

    公开(公告)日：2001-01-18

    申请号：DE69424523

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.

    37.
    发明专利
    未知

    公开(公告)号：DE69424771T2

    公开(公告)日：2000-10-26

    申请号：DE69424771

    申请日：1994-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

    IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

    Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

    38.
    发明专利
    未知

    公开(公告)号：DE69424771D1

    公开(公告)日：2000-07-06

    申请号：DE69424771

    申请日：1994-03-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  OLIVO MARCO ,  PADOAN SILVIA

    IPC: G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

    Abstract: A device (20) including a load (27) connected by a selection circuit (4) to a number of bit lines (2), and a load (32, 33) connected to a reference cell (17), for detecting the current in the selected bit line (2) and in the reference cell. The load connected to the bit lines comprises a transistor (27), and the reference load comprises two current paths (32a, 33a), each formed by one transistor (32, 33). One (32) of the two transistors is diode-connected, and the other (33) is switchable by a switching network (35-50) connected to the gate terminal (34) of the respective transistor (33), for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

    39.
    发明专利
    未知

    公开(公告)号：DE69324020T2

    公开(公告)日：1999-07-15

    申请号：DE69324020

    申请日：1993-12-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G06F11/20

    Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements, comprises a plurality of programmable non-volatile memory registers (1), which are programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements; the redundancy circuitry comprises combinatorial circuit means (3) supplied by address signals (ADD) and supplying the non-volatile registers (1) with an inhibition signal (DIS) for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register (1).

    40.
    发明专利
    未知

    公开(公告)号：DE69324020D1

    公开(公告)日：1999-04-22

    申请号：DE69324020

    申请日：1993-12-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G06F11/20

    Abstract: A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements, comprises a plurality of programmable non-volatile memory registers (1), which are programmable to store addresses of defective memory elements which must be replaced by redundancy memory elements; the redundancy circuitry comprises combinatorial circuit means (3) supplied by address signals (ADD) and supplying the non-volatile registers (1) with an inhibition signal (DIS) for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register (1).

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