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    31.
    发明专利
    未知

    公开(公告)号：DE69424523D1

    公开(公告)日：2000-06-21

    申请号：DE69424523

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: A circuit (1) generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit (1) includes a variable, asymmetrical propagation line (5, 37) composed of a succession of elementary delay elements (6-8, 38, 40) enabled or disabled on the basis of memorized logic signals (TIMS, PCS, DETS), the state of which is determined when debugging the memory (100) in which the circuit (1) is implemented.

    33.
    发明专利
    未知

    公开(公告)号：DE69325277T2

    公开(公告)日：2000-01-20

    申请号：DE69325277

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  OLIVO MARCO ,  GOLLA CARLA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: A circuit for detecting a threshold voltage in storage devices integrated to a semiconductor, for which a power supply above a certain value is provided, is of the type which comprises a comparator (3) connected between a voltage supply line (2) and a signal ground (GND) and having a first or reference input (I1) and a second or signal input (I2), and comprises a generator (8) of a stable voltage reference (RIF) having an output connected to the first input (I1) and a divider (9) of a supply voltage (Vdd) connected to the second input (I2) of the comparator (3). A circuit means is arranged to feed the voltage line (2) with the higher of the supply voltage (Vdd) value and the value of a programming voltage (Vpp) of the storage device.

    34.
    发明专利
    未知

    公开(公告)号：DE69419403T2

    公开(公告)日：1999-12-30

    申请号：DE69419403

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

    Abstract: A load timing circuit (20) including an out-like circuit (21) identical to the output circuits of the memory, so as to present the same propagation time; a simulating signal source (34) for generating a data simulating signal (SP); a synchronizing network (30, 32) for detecting a predetermined switching edge of the data simulating signal (SP) and enabling (35) supply of the signal to the out-like circuit (21) and data supply to the output circuits of the memory; a combinatorial network (29, 30) for detecting propagation of the data simulating signal (SP) to the output of the out-like circuit and disabling the data simulating signal (SP); and a reset element (33) for resetting the timing circuit (20).

    35.
    发明专利
    未知

    公开(公告)号：DE69325587T2

    公开(公告)日：1999-12-23

    申请号：DE69325587

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C11/00

    Abstract: A count unit (1) for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter (8) and a number of registers (9, 10) equal in number to the count functions involved. The registers (9, 10) store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter (8) which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One (10) of the registers presents a second parallel input (ADDR) for externally loading an initial data which may be transferred to the other registers (9) via the counter (8).

    36.
    发明专利
    未知

    公开(公告)号：DE69325458D1

    公开(公告)日：1999-07-29

    申请号：DE69325458

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  PADOAN SILVIA

    IPC: G06F1/24 ,  G11C17/00 ,  G11C16/06 ,  G11C16/30

    Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device (1) of a type which comprises a matrix (2) of memory cells and a control logic portion (3) being supplied a supply voltage (Vcc) and a programming voltage (Vpp), and a threshold detection circuit (5) adapted to detect a decrease in the supply voltage (Vcc), provides for the signal applied to the control logic (3) to be obtained as a change-over function between the output signal from the threshold detector (5) and a reset signal (POR) generated during the power-on transient of the device.

    37.
    发明专利
    未知

    公开(公告)号：DE69324258D1

    公开(公告)日：1999-05-06

    申请号：DE69324258

    申请日：1993-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： OLIVO MARCO ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  H03K21/38 ,  H03K19/21 ,  G11C16/06

    Abstract: An end-of-count detecting device (1) for nonvolatile memories, comprising a decoder (2) in the form of a wired OR structure of a number of transistors (3) of the same type, the gate terminals of which are fed with a count signal generated by a counter element (6) and having a predetermined end-of-count value to be detected. A load (7), which may be static, pseudo-dynamic or dynamic, is provided between the common node (4) of the decoder transistors (3) and a reference potential line (VDD); and the decoder output (4) formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.

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