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    32.
    发明专利
    未知

    公开(公告)号：DE69624460D1

    公开(公告)日：2002-11-28

    申请号：DE69624460

    申请日：1996-01-26

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： ALINI ROBERTO ,  BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  PISATI VALERIO

    IPC: H03F3/30 ,  H03F3/34 ,  H03F1/00

    Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).

    33.
    发明专利
    未知

    公开(公告)号：DE69327053T2

    公开(公告)日：2000-02-24

    申请号：DE69327053

    申请日：1993-09-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

    Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

    34.
    发明专利
    未知

    公开(公告)号：DE69421071D1

    公开(公告)日：1999-11-11

    申请号：DE69421071

    申请日：1994-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B20/10

    Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

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