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公开(公告)号：US20230389172A1
公开(公告)日：2023-11-30
申请号：US18447265
申请日：2023-08-09
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Heng-Ming Nien , Ching-Sheng Chen , Ching Chang , Ming-Ting Chang , Chi-Min Chang , Shao-Chien Lee , Jun-Rui Huang , Shih-Lian Cheng
Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.
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公开(公告)号：US11818833B2
公开(公告)日：2023-11-14
申请号：US17867624
申请日：2022-07-18
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
IPC: H05K1/02 , H01L23/498 , H05K1/14
CPC classification number: H05K1/0222 , H01L23/49822 , H01L23/49833 , H05K1/024 , H05K1/144 , H05K2201/098 , H05K2201/0959 , H05K2201/09672
Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.
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公开(公告)号：US11785707B2
公开(公告)日：2023-10-10
申请号：US17496791
申请日：2021-10-08
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Heng-Ming Nien , Ching-Sheng Chen , Ching Chang , Ming-Ting Chang , Chi-Min Chang , Shao-Chien Lee , Jun-Rui Huang , Shih-Lian Cheng
CPC classification number: H05K1/0222 , H05K1/113 , H05K1/119 , H05K3/429 , H05K3/462 , H05K1/181 , H05K3/0094 , H05K3/24 , H05K2201/10734
Abstract: Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
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公开(公告)号：US11686008B2
公开(公告)日：2023-06-27
申请号：US17745809
申请日：2022-05-16
Applicant: Unimicron Technology Corp.
Inventor： Heng-Ming Nien , Chih-Chiang Lu , Cho-Ying Wu , Shih-Lian Cheng
CPC classification number: C25D5/007 , C25D17/007
Abstract: An electroplating apparatus including an anode and a cathode, a power supply, and a regulating plate is provided. The power supply is electrically connected to the anode and the cathode. The regulating plate is arranged between the anode and the cathode. The regulating plate includes an insulating grid plate and a plurality of magnetic components. The plurality of magnetic components are uniformly and randomly arranged on the insulating grid plate. An electroplating method is also provided.
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公开(公告)号：US20230156918A1
公开(公告)日：2023-05-18
申请号：US17853933
申请日：2022-06-30
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
CPC classification number: H05K1/116 , H05K1/0222 , H05K2201/09509 , H05K2201/0195
Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.
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Patent Agency Ranking
公开(公告)号：US20230156908A1
公开(公告)日：2023-05-18
申请号：US17867624
申请日：2022-07-18
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
IPC: H05K1/02 , H01L23/498 , H05K1/14
CPC classification number: H05K1/0222 , H01L23/49833 , H01L23/49822 , H05K1/144 , H05K1/024 , H05K2201/09672 , H05K2201/098 , H05K2201/0959
Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.
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公开(公告)号：US10512166B2
公开(公告)日：2019-12-17
申请号：US15273727
申请日：2016-09-23
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
Abstract: A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.
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公开(公告)号：US10426038B2
公开(公告)日：2019-09-24
申请号：US15256759
申请日：2016-09-06
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
Abstract: A manufacturing method of a circuit board and a stamp are provided. The method includes: forming a circuit pattern and a dielectric layer on a dielectric substrate; forming a conductive via in the dielectric layer; forming a thermal-sensitive adhesive layer on the dielectric layer; forming a photoresist material layer on the thermal-sensitive adhesive layer; imprinting the photoresist material layer using a stamp, wherein a first conductive layer is disposed on the surface of the pressing side of the stamp, a second conductive layer is disposed on the surface of the other portions; applying a current to the stamp; removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and thermal-sensitive adhesive layer; forming a patterned metal layer on the region exposed by the patterned photoresist layer; removing the patterned photoresist layer and thermal-sensitive adhesive layer.
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公开(公告)号：US10098234B2
公开(公告)日：2018-10-09
申请号：US15252247
申请日：2016-08-31
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
Abstract: A manufacturing method of a circuit board and a piezochromic stamp are provided. A circuit pattern is formed on a dielectric substrate. A dielectric layer having a hole or a conductive via and covering the circuit pattern is formed on the dielectric substrate. A conductive seed layer is formed on the dielectric layer. A photoresist layer is formed on the conductive seed layer. A piezochromic stamp is imprinted on the photoresist layer, wherein when the pressing side of the piezochromic stamp is in contact with the conductive seed layer, the light transmittance effect thereof is changed to blocking or allowing light having a specific wavelength to pass through. A patterned photoresist layer is formed by using the piezochromic stamp as a mask. A patterned metal layer is formed on the exposed conductive seed layer. The patterned photoresist layer and the conductive seed layer are removed.
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40.发明申请公开(公告)号：US20180070452A1
公开(公告)日：2018-03-08
申请号：US15256757
申请日：2016-09-06
Applicant: Unimicron Technology Corp.
Inventor： Pu-Ju Lin , Shih-Lian Cheng , Yu-Hua Chen , Cheng-Ta Ko , Jui-Jung Chien , Wei-Tse Ho
IPC: H05K3/06 , H05K3/10 , H05K3/42 , H05K3/24 , G03F7/16 , G03F7/20 , G03F7/09 , G03F7/32 , G03F7/40 , G03F1/50 , G03F1/76
CPC classification number: G03F1/50 , G01K7/24 , G01K15/007 , G03F7/2032 , G03F7/2047 , H05K3/0023 , H05K3/064 , H05K3/107 , H05K3/1275 , H05K3/182 , H05K3/241 , H05K3/422
Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
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