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    박막구조체 및 그 제조방법
    33.
    发明公开
    박막구조체 및 그 제조방법 有权
    박막구조체및그제조방법

    公开(公告)号：KR1020030043972A

    公开(公告)日：2003-06-02

    申请号：KR1020037004373

    申请日：2001-07-26

    Applicant: 미쓰비시덴키 가부시키가이샤

    Inventor： 오쿠무라미카 ,  호리카와마키오 ,  이시바시키요시

    IPC: H01L21/20

    CPC classification number: H01L21/02255 ,  B81B2201/0235 ,  B81B2203/0307 ,  B81B2207/07 ,  B81C1/00365 ,  B81C2201/0178 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31662

    Abstract: 본 발명은, 기판 및 그 제조방법 및 박막구조체에 관한 것으로, 열수축시에 기판의 산화막과 그 산화막 상에 형성되는 다른 막과의 사이에 생기는 응력차를 감소할 수 있음과 동시에, 후막의 산화막을 형성할 때의 막형성에 요하는 시간을 단축할 수 있는 기판 및 그 제조방법 및 박막구조체를 제공하는 것을 목적으로 한다. 그리고, 상기목적을 달성하기 위해, 이 기판(1)이, 실리콘에 의해 형성된 기판 본체(31)와, 그 위에 형성된 베이스용의 산화막(33)을 구비하고 있다. 산화막(33)은, 기판 본체(31)중의 실리콘이 열산화된 형성된 열 SiO
    2 막으로 이루어지는 제1 산화막(61)과, 그 위에 적층되어 형성된 고온산화막으로 이루어지는 제2 산화막(63)을 구비하고 있다.

    Abstract translation: 基板具备由硅构成的基板主体和在其上形成的基台用氧化膜。 氧化物膜包括主要由通过热氧化衬底主体中的硅而形成的热SiO 2 SUB / SUB膜和由高温氧化物膜制成的第二氧化物膜制成的第一氧化物膜以及 在其上形成。 或者，第二氧化物膜可以由TEOS形成。

    Pseudo SOI process
    36.
    发明授权
    Pseudo SOI process 有权

    公开(公告)号：US10053360B1

    公开(公告)日：2018-08-21

    申请号：US15685879

    申请日：2017-08-24

    Applicant: Kionix, Inc.

    Inventor： Martin Heller

    IPC: H01L21/00 ,  B81C1/00

    CPC classification number: B81C1/00047 ,  B81C1/00095 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2201/0132 ,  B81C2201/0171 ,  B81C2201/0178

    Abstract: A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.

    Constrained Oxidation of Suspended Micro- and Nano-Structures
    38.
    发明申请
    Constrained Oxidation of Suspended Micro- and Nano-Structures 有权
    悬浮微米和纳米结构的约束氧化

    公开(公告)号：US20110207335A1

    公开(公告)日：2011-08-25

    申请号：US12709981

    申请日：2010-02-22

    Applicant: Tymon Barwicz

    Inventor： Tymon Barwicz

    IPC: H01L21/316

    CPC classification number: H01L29/0665 ,  B81B2203/0109 ,  B81C1/00833 ,  B81C2201/0178 ,  B81C2201/053 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

    Abstract: Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.

    Abstract translation: 提供了用于在氧化期间防止悬浮的微/纳米结构的弯曲/屈曲的技术。 一方面，提供一种氧化结构的方法。 该方法包括提供具有至少一个悬浮元素的结构，所述悬浮元素选自：微结构，纳米结构及其组合; 围绕包层材料中的至少一个悬挂元件; 以及通过所述包层材料氧化所述至少一个悬浮元件，其中所述包层材料物理地约束并由此防止所述至少一个悬浮元件在氧化期间的变形。

    Method and apparatus for preventing metal/silicon spiking in MEMS devices
    39.
    发明申请
    Method and apparatus for preventing metal/silicon spiking in MEMS devices 审中-公开
    用于防止MEMS器件中金属/硅尖峰的方法和装置

    公开(公告)号：US20060110842A1

    公开(公告)日：2006-05-25

    申请号：US10996234

    申请日：2004-11-23

    Applicant: Yuh-Hwa Chang ,  Fei-Yun Chen ,  Jiann-Tyng Tzeng ,  Cheng-Yu Chu ,  Chun-Kai Peng ,  Chih-Chieh Yeh ,  Chih-Heng Po ,  Dah-Chuen Ho

    Inventor： Yuh-Hwa Chang ,  Fei-Yun Chen ,  Jiann-Tyng Tzeng ,  Cheng-Yu Chu ,  Chun-Kai Peng ,  Chih-Chieh Yeh ,  Chih-Heng Po ,  Dah-Chuen Ho

    IPC: H01L21/00 ,  H01L31/0203

    CPC classification number: B81C1/00253 ,  B81C2201/0178 ,  B81C2201/053

    Abstract: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include one or more metal or metallic alloys. To prevent spiking from the MEMS component, the sides thereof can be coated with one ore more spacer or barrier layers. In one embodiment, oxygen plasma and thermal oxidation methods are used to deposit spacers. In another embodiment, an oxide layer is deposited over the wafer, covering the substrate and the MEMS component. Selective etching or anisotropic etching can be used to remove the oxide layer from certain regions of the MEMS and the substrate while covering the sidewalls. An amorphous silicon layer can then be deposited to cover the MEMS device.

    Abstract translation: 本公开涉及一种用于防止金属原子从金属化层挤出或尖峰到硅晶片其它层的方法和装置。 在一个实施例中，该方法包括在衬底上形成具有MEMS部件的在船上的硅装置。 MEMS组件可以包括一种或多种金属或金属合金。 为了防止从MEMS部件尖尖，其侧面可以涂覆一个或多个间隔物或阻挡层。 在一个实施例中，使用氧等离子体和热氧化方法来沉积间隔物。 在另一个实施例中，氧化物层沉积在晶片上，覆盖衬底和MEMS部件。 可以使用选择性蚀刻或各向异性蚀刻从覆盖侧壁的MEMS和衬底的某些区域去除氧化物层。 然后可以沉积非晶硅层以覆盖MEMS器件。

    Method of smoothing a trench sidewall after a deep trench silicon etch process
    40.
    发明授权
    Method of smoothing a trench sidewall after a deep trench silicon etch process 失效
    在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法

    公开(公告)号：US06846746B2

    公开(公告)日：2005-01-25

    申请号：US10137543

    申请日：2002-05-01

    Applicant: Michael Rattner ,  Jeffrey D. Chinn

    Inventor： Michael Rattner ,  Jeffrey D. Chinn

    IPC: B81C1/00 ,  H01L21/3065 ,  H01L21/302

    CPC classification number: B81C1/00611 ,  B81B2203/033 ,  B81C2201/0126 ,  B81C2201/0178 ,  H01L21/3065 ,  H01L21/30655

    Abstract: Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.

    Abstract translation: 这里公开了一种在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法，其最小化在硅沟槽蚀刻之后存在的侧壁扇形。 该方法包括将硅沟槽侧壁暴露于在约1mTorr至约30mTorr范围内的处理室压力下从含氟气体产生的等离子体，时间范围为约10秒至约600 秒。 在本发明的蚀刻后处理方法的执行期间，施加约-10V至约-40V范围内的衬底偏置电压。

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