公开(公告)号：JPH1186585A

公开(公告)日：1999-03-30

申请号：JP19795098

申请日：1998-06-09

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  HULL RICHARD L

IPC: G11C16/02 ,  G11C7/06 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To improve high speed reading of a memory cell by providing a pre-charge device for rising a voltage level of a column of a memory array and connecting a state control circuit to monitor and control an output voltage of the pre-charge device. SOLUTION: Voltages in connecting points 44, 42 are in a grounding voltage when the input of an input terminal 40 is low, the output of a first NAND gate 48 is high, and a pre-charge transistor 54 is kept in an inactive state. An input voltage is risen, the pre-charge transistor 54 is activated, and the voltage an the connecting point 44 begins to rise toward VDD. When a transistor bias device 49 exists within a self timing pre-charge sense amplifier 30, the voltage in the connecting point 42 begins to rise toward VBIAS at the time point wherein the pre-charge transistor 54 becomes an active state. A sense amplifier 56 is connected for monitoring the output voltage, and the high speed reading is executed with the memory cell 32.

公开(公告)号：JP2002189537A

公开(公告)日：2002-07-05

申请号：JP2001276540

申请日：2001-09-12

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L

IPC: G01R19/165 ,  G06F1/24 ,  G06F1/28 ,  G06F1/30 ,  G06F11/30 ,  G06F15/78 ,  H02H3/247

Abstract: PROBLEM TO BE SOLVED: To provide a blown-out detection circuit capable of analyzing the features of power supply voltage dip, and collating it with a prescribed reference and hysteresis, and deciding whether or not reset should be started each time the power supply voltage is made less than a threshold level. SOLUTION: A microcontroller device controls an external system set on the same circuit as that of the device. A microcontroller is provided with a CPU 10, a program memory 12, a data memory 13, and various peripheral elements. A blown-out protection circuit 16 monitors the power supply voltage level for a chip, and when the difference between the power supply voltage and a ground reference level becomes less than a threshold operating voltage level, resets the device, and operates so that the malfunction of the device can be prevented. The operation of the device is stopped when reset while status of implementation of a program instruction by the CPU 10 and data stored in the data memory 13 are maintained as they are when the device is reset.

公开(公告)号：JP2001319487A

公开(公告)日：2001-11-16

申请号：JP2001083671

申请日：2001-03-22

Applicant: MICROCHIP TECH INC

Inventor： GERBER DONALD S ,  HEWITT KENT D ,  DAVIES DAVID M ,  SHELDS JEFFREY

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for making the array of memory cells compact and compressing a memory cell densely. SOLUTION: This method is a method for operating memories including memory cells of the first and the second groups. The first group cells formed in a first semiconductor region are connected effectively to word lines and individual bit line, and the second group cells formed in a second semiconductor region are connected effectively to word lines and individual bit liens. This method includes a process applying first voltage to the word lines, a process applying second voltage to the first semiconductor region, a process applying selected voltage the bit lines of the first group cells, a process applying fourth voltage to the second semiconductor region, and a process applying fifth voltage to the bit lines of the second group cells.

公开(公告)号：JP2001308656A

公开(公告)日：2001-11-02

申请号：JP2001094420

申请日：2001-03-28

Applicant: MICROCHIP TECH INC

Inventor： NOLAN JIM

IPC: H03F1/52 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To manufacture an operational amplifier, having a phase reversal protection circuit, using a complementary metal oxide semiconductor(CMOS) process. SOLUTION: The integrated circuit operational amplifier having output phase reversal protection comprises an operational amplifier having differential inputs, where one of the differential inputs is a positive input, and the other differential input is a negative input; a first comparator having a positive sense input, a negative sense input and an output; and a second comparator having a positive sense input, a negative sense input and an output, where the first comparator output is connected to first logic circuits of the operational amplifier, such that when the first comparator output is at the second logic level the output of the operational amplifier is lowered to the minimum voltage level, and the second comparator output is connected to second logic circuits of the operational amplifier, such that when the second comparator output is at the second logic level the output of the operational amplifier is raised to a maximum voltage level.

公开(公告)号：JP2001244816A

公开(公告)日：2001-09-07

申请号：JP2001017697

申请日：2001-01-25

Applicant: MICROCHIP TECH INC

Inventor： BRUNOLLI MICHAEL ,  HOANG CHINH

IPC: H03M1/76 ,  H03M1/66 ,  H03M1/68

Abstract: PROBLEM TO BE SOLVED: To provide a simple and economical digital potentiometer which has improved linearity and a shortened setting time when the resistance is changed by switching. SOLUTION: This potentiometer is equipped with plural 1st switches connected to a 1st input node, plural 2nd switched connected to a 2nd input node, plural 3rd switches connected to an output node, and 1st, 2nd, and 3rd strings of series-connected resistors; and the 1st string is connected between the 1st string and 2nd string, the 1st switches between the 1st input node and the 1st string of the resistors, the 2nd switches between the 2nd input node and the 2nd string of the resistors, and the 3rd switches between the output node and the 3rd string of the resistors.

公开(公告)号：JP2000235435A

公开(公告)日：2000-08-29

申请号：JP26118099

申请日：1999-09-14

Applicant: MICROCHIP TECH INC

Inventor： SMIT WILLEM ,  DIPPENAAR THEODOR JOHANNES ,  SCHIEKE PETER

IPC: G06F1/28 ,  G05F1/10 ,  G06F1/26 ,  H02J1/00

Abstract: PROBLEM TO BE SOLVED: To prevent an improper operation resulted from a voltage drop compensation level excessively set high due to an improper instruction or firmware error. SOLUTION: This microprocessor power source system is provided with a programmable power source 30 for supplying a power to a microprocessor, a programmable voltage drop detector 20 connected with the programmable power source for detecting a case that an operating voltage is made lower than a voltage drop reference voltage, and for providing a voltage drop signal output, and a control unit 40 connected with the programmable power source and the programmable voltage drop detector for setting the operating voltage and the voltage drop reference voltage.

公开(公告)号：JPH11316679A

公开(公告)日：1999-11-16

申请号：JP30756198

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： WOJEWODA IGOR ,  DRAKE RODNEY J ,  MITRA SUMIT

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F12/06

Abstract: PROBLEM TO BE SOLVED: To encode many addressing modes and also to have many bank address value generation sources by preparing a data memory having plural data banks, a selection circuit which selects one of bank address value generation sources, a bank selection register and an instruction register. SOLUTION: A data memory 12 is connected to a CPU to store and transfer data. One of plural banks of the memory 12 serves as a general-purpose/special register. A selection circuit 14 selects one of many bank address value generation sources. A bank selection register 18 supplies a bank address value for an instruction that is executed in a direct short addressing mode. An instruction register 22 supplies a bank address value for an instruction that is executed in a direct long addressing mode and also supplies a bank address value for an instruction that is executed in a direct short addressing mode.

公开(公告)号：JPH11265287A

公开(公告)日：1999-09-28

申请号：JP30756398

申请日：1998-10-28

Applicant: MICROCHIP TECH INC

Inventor： ALLEN STEPHEN ,  WOJEWODA IGOR

IPC: G06F9/42 ,  G06F7/78 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To make predecodable the decrement value of a stack memory by selecting one of the next unused position in a stack memory device or a position immediately before the next unused position in the stack memory. SOLUTION: The stack pointer 12 is used for generating the next unused position in the stack memory device and indicating a place to write a present value in a program counter. The stack pointer 12 further generates the position immediately before the next unused position and reads the final value of the program counter written in the stack memory device. The next unused position in the stack memory device is selected for a write operation and the position immediately before the next unused position in the stack memory device is selected for a read operation. After executing a present instruction, the stack point 12 further performs one of the post increment or post decrement operations at the next unused position in the stack memory.

公开(公告)号：JPH11212787A

公开(公告)日：1999-08-06

申请号：JP30613498

申请日：1998-10-27

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: PROBLEM TO BE SOLVED: To maximize the number of usable operation codes and addressable registers and also to enable a multiple addressing mode by having an instruction set which can realize an addressing mode in which plural instructions are different from each other. SOLUTION: An instruction 30 includes plural bits 32. The bits 32 are divided into an operation code field 34 that shows what type of an operation is performed, a destination bit 36 that shows where operation results are stored and a register address field 38 which shows a register where the instruction 30 is operated or the address of variable data. The lengths of the fields 34 and 38 are determined by the number of operation codes a user desires to realize or the number of addressable registers. Virtual register address positions in a processor architecture system used together with the instruction 30 respectively start an indirect addressing mode when they are accessed.

公开(公告)号：JPH11163123A

公开(公告)日：1999-06-18

申请号：JP25162198

申请日：1998-09-04

Applicant: MICROCHIP TECH INC

Inventor： AMAND ROGER D ST ,  DEUTSCHER NEIL F ,  MA ROBERT P

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a narrow thermally oxidized silicon side isolation region in a semiconductor substrate and a MOS or CMOS device. SOLUTION: After a process has been performed for removing bottom sections of openings 20 of a silicon nitride layer 16 and an amorphous polysilicon layer 14, the exposed parts are removed by using the silicon nitride layer 16 as a mask. Then narrow oxidized silicon side isolation regions are grown in the surface of a semiconductor substrate by heating through an opening formed via an oxynitride layer 12. Then the semiconductor substrate is left in such a state that the substrate has the narrow oxidized silicon side isolation regions and the remaining surface section of the substrate is exposed by removing the parts of the silicon nitride layer 16, the amorphous polysilicon layer 14, and the oxynitride layer 12. Following this, a MOS semiconductor device is formed between the narrow oxidized silicon side isolation regions formed in the semiconductor substrate.