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公开(公告)号：KR1020070088074A
公开(公告)日：2007-08-29
申请号：KR1020060018219
申请日：2006-02-24
Applicant: 삼성전기주식회사
IPC: H05K3/42
CPC classification number: H05K3/423 , H05K3/427 , H05K3/4602 , H05K2201/09563 , H05K2203/1476 , Y10T29/49126 , Y10T29/49155
Abstract: A PCB(Printed Circuit Board) with an IVH(Inner Via Hole) and a manufacturing method thereof are provided to prevent the deterioration of agitation characteristics by applying current at both surfaces of a core layer asymmetrically. A PCB with an IVH(300) includes a core layer(310), a first coating layer(330), and a second coating layer(340). The core layer(310) has the IVH(300) at a predetermined position. The core layer(310) is composed of an insulating layer(313) and a copper film(320a,320b) covered on the insulated layer(313). The first coating layer(330) has an extra space inside the IVH(300) by blocking one side of the IVH(300). The second coating layer(340) blocks the other side of the IVH(300) and fills the extra space. The extra space has a cone shape.
Abstract translation: 提供具有IVH（内部通孔）的PCB（印刷电路板）及其制造方法，以通过不对称地在芯层的两个表面上施加电流来防止搅拌特性的劣化。 具有IVH（300）的PCB包括芯层（310），第一涂层（330）和第二涂层（340）。 核心层（310）在预定位置具有IVH（300）。 芯层（310）由绝缘层（313）和覆盖在绝缘层（313）上的铜膜（320a，320b）构成。 通过阻止IVH（300）的一侧，第一涂层（330）在IVH（300）内部具有额外的空间。 第二涂层（340）阻挡IVH（300）的另一侧并填充额外的空间。 额外的空间有锥形。
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公开(公告)号：KR1020150083344A
公开(公告)日：2015-07-17
申请号：KR1020140002979
申请日：2014-01-09
Applicant: 삼성전기주식회사
IPC: H05K3/46
Abstract: 본발명은인쇄회로기판및 인쇄회로기판의제조방법에관한것이다. 본발명의실시예에따른인쇄회로기판은관통비아홀이형성된절연층, 관통비아홀에형성되며, 시드층및 시드층에형성된도금층을포함하는관통비아, 및절연층의상부및 하부중 적어도하나에형성되며, 시드층및 도금층을포함하는회로층을포함할수 있다.
Abstract translation: 印刷电路板及其制造方法技术领域本发明涉及印刷电路板及其制造方法。 根据本发明的实施例，印刷电路板包括：绝缘层，其包括通孔; 在通孔中形成的贯通孔，其包括种子层和形成在种子层中的镀层; 以及电路层，其形成在绝缘层的上部或下部的至少一个中，并且包括种子层和电镀层。
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公开(公告)号：KR1020150054171A
公开(公告)日：2015-05-20
申请号：KR1020130136274
申请日：2013-11-11
Applicant: 삼성전기주식회사
IPC: H05K3/46
CPC classification number: H05K1/0271 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/12042 , H01L2924/15311 , H05K3/002 , H05K3/0029 , H05K3/0047 , H05K3/0052 , H05K3/007 , H05K3/429 , H05K3/4605 , H05K3/4644 , H05K2201/017 , H05K2201/0187 , H05K2201/0195 , H05K2201/0909 , H05K2201/09136 , H05K2201/09827 , H05K2201/09881 , H05K2201/2009 , H05K2203/1536 , H01L2224/81 , H01L2924/00 , H05K3/46 , H05K3/40
Abstract: 본발명은인쇄회로기판및 그제조방법에관한것이다. 본발명의인쇄회로기판은, 글라스재질의코어; 상기코어의측면을비롯한외주면전체를감싸는절연층; 상기절연층상에형성된내부회로층; 및상기코어와절연층을관통하여상기내부회로층을연결하는비아; 를포함한다.
Abstract translation: 印刷电路板及其制造方法技术领域本发明涉及印刷电路板及其制造方法。 本发明的印刷电路板包括：玻璃材料芯; 覆盖包括芯的侧面的整个外周表面的绝缘层; 形成在绝缘层上的内部电路层; 以及穿过芯部和绝缘层的通孔，并且连接内部电路层。
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公开(公告)号：KR1020120053735A
公开(公告)日：2012-05-29
申请号：KR1020100115007
申请日：2010-11-18
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A printed circuit board and a method for filling a via hole thereof are provided to efficiently fill inside a via hole without dimples. CONSTITUTION: A base substrate(110) is provided to manufacture a printed circuit board(100). A copper-clad laminate having copper layers(110b,110c) of a thin film is provided to both sides by interposing an insulating layer(110a). A via hole(120) to be formed is partitioned into a predetermined number on the base substrate. A first separated via is formed by primarily processing a part of the partitioned via hole. The first separated via is filled with a metal. A second separated via is formed by secondarily processing the rest of the partitioned via hole. The via hole is filled by filling the second separated via with the metal.
Abstract translation: 目的：提供印刷电路板和填充其通孔的方法，以有效地填充没有凹坑的通孔内部。 构成：提供基底（110）以制造印刷电路板（100）。 通过插入绝缘层（110a）将具有薄膜的铜层（110b，110c）的覆铜层压板设置在两侧。 要形成的通孔（120）在基底基板上划分成预定数量。 通过主要处理分隔的通孔的一部分来形成第一分离的通孔。 第一个分离的通孔用金属填充。 通过二次处理其余分隔的通孔来形成第二分离的通孔。 通过用金属填充第二分离的通孔来填充通孔。
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公开(公告)号：KR101128559B1
公开(公告)日：2012-03-23
申请号：KR1020100089406
申请日：2010-09-13
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A via hole formation method of a printed circuit substrate is provided to easily arrange a plating layer within a via-hole by combining a conductive post and a base substrate in which the via-hole is formed. CONSTITUTION: A via hole is formed by punching a base substrate(S100). A conductive post is arranged on a carrier(S110). The base substrate in which the via hole is formed is combined with the carrier in which the conductive post is arranged(S120). The inside of the via hole is filled with plug(S130). The carrier is eliminated(S140). The upper surface and the lower surface of the base substrate is buffed and polished(S150). A desmear process and a plating process are performed on the upper surface and lower surface of the base substrate(S160). A circuit is formed on the plated base substrate(S170).
Abstract translation: 目的：提供印刷电路基板的通孔形成方法，通过组合形成通孔的导电柱和基底基板，容易地在通孔内布置镀层。 构成：通过冲压基底基板形成通孔（S100）。 导电柱布置在载体上（S110）。 其中形成通孔的基底基板与布置导电柱的载体（S120）组合。 通孔的内部填充有塞子（S130）。 载体被消除（S140）。 基底基板的上表面和下表面被抛光抛光（S150）。 在基板的上表面和下表面上进行去污处理和电镀处理（S160）。 在电镀基板上形成电路（S170）。
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Patent Agency Ranking
公开(公告)号：KR1020120024219A
公开(公告)日：2012-03-14
申请号：KR1020100086999
申请日：2010-09-06
Applicant: 삼성전기주식회사
CPC classification number: H05K3/0097 , C25D5/022 , H05K3/18 , H05K2201/09781
Abstract: PURPOSE: A substrate plating method and a circuit board manufacturing method using the same are provided to minimize plating deviation caused by the effect of a dummy area in a circuit board arranged on the perimeter of a panel substrate. CONSTITUTION: A circuit board manufacturing method comprise the steps of: preparing a panel substrate(5) divided into a circuit board area and a dummy area, calculating the area ratio of a circuit pattern in the circuit board area, determining the ratio of a plated area in the dummy area in consideration of a plating area ratio of the circuit board area, setting a plated part in the circuit board are and the dummy area, and electroplating the panel substrate to form the circuit pattern.
Abstract translation: 目的：提供一种基板镀覆方法和使用该方法的电路板制造方法，以最小化由布置在面板基板的周边上的电路板中的虚拟区域的影响引起的电镀偏差。 构成：一种电路板制造方法，包括以下步骤：制备划分为电路板区域和虚拟区域的面板基板（5），计算电路板区域中的电路图案的面积比，确定镀覆 考虑到电路板面积的电镀面积比，设置电路板中的电镀部分和虚拟区域，并且将面板基板电镀以形成电路图案，在虚拟区域中的面积。
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公开(公告)号：KR101085476B1
公开(公告)日：2011-11-21
申请号：KR1020100104058
申请日：2010-10-25
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A manufacturing method for a printed circuit board is provided to reduce a short circuit due to etchant penetration by removing a seed layer having high resistance against oxidation. CONSTITUTION: A manufacturing method for a printed circuit board is comprised of steps: preparing a metal laminated plate on the surface of an insulating layer(S110); manufacturing a hole in the metal laminated plate(S120); forming a seed layer on the inner wall of the hole and the surface of a metal layer(S130); forming a etching resist in the metal laminated plate(S140); removing the seed layer which is formed in the surface of the metal layer(S150); removing a plating resist(S190); and etching the metal layer(S200).
Abstract translation: 目的：提供一种用于印刷电路板的制造方法，以通过去除具有高抗氧化性的种子层来减少由蚀刻剂渗透引起的短路。 构成：印刷电路板的制造方法包括以下步骤：在绝缘层的表面上制备金属层压板（S110）; 在金属层压板上制造孔（S120）; 在孔的内壁和金属层的表面上形成种子层（S130）; 在金属层压板中形成抗蚀剂（S140）; 去除在金属层的表面形成的种子层（S150）; 去除电镀抗蚀剂（S190）; 并蚀刻金属层（S200）。
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公开(公告)号：KR101081588B1
公开(公告)日：2011-11-08
申请号：KR1020100075011
申请日：2010-08-03
Applicant: 삼성전기주식회사
CPC classification number: H05K3/108 , H05K3/387 , H05K2203/1152 , H05K2203/1157
Abstract: PURPOSE: A method for forming plating layer and a method for manufacturing circuit board using the same are provided to prevent no-plating by removing an anti-corrosive material remaining in a primer resin. CONSTITUTION: In a method for forming plating layer and a method for manufacturing circuit board using the same, a metal film coated with a primer resin is provided in one side(S110). The primer resin layer is formed by using the illuminance of a metal film(S120). The metal film is laminated on the insulating layer so that the primer resin layer is attached to an insulating layer(S122). The metal film is removed through etching(S124). The primer resin layer is restored to remove the metal film of anti-corrosive material remaining the primer resin layer(S130). A circuit pattern is formed in the primer resin(S140).
Abstract translation: 目的：提供一种形成镀层的方法和使用该方法制造电路板的方法，以通过去除残留在底漆树脂中的防腐蚀材料来防止不镀。 构成：在形成镀层的方法和使用其的电路板的制造方法中，在一侧设置涂布有底漆树脂的金属膜（S110）。 底漆树脂层通过使用金属膜的照度形成（S120）。 将金属膜层叠在绝缘层上，使底漆树脂层附着在绝缘层上（S122）。 金属膜通过蚀刻去除（S124）。 恢复底漆树脂层以去除残留底漆树脂层的防腐蚀材料的金属膜（S130）。 在底漆树脂中形成电路图案（S140）。
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公开(公告)号：KR1020090108826A
公开(公告)日：2009-10-19
申请号：KR1020080034134
申请日：2008-04-14
Applicant: 삼성전기주식회사 , 삼성엘이디 주식회사
CPC classification number: C01B13/14 , B82Y30/00 , B82Y40/00 , C01G41/00 , C01P2004/64
Abstract: PURPOSE: A method for preparing metal chalcogenide nanoparticles and metal chalcogenide nanoparticles prepared by the same are provided to prepare various shaped metal chalcogenide nanoparticles. CONSTITUTION: A method for preparing metal chalcogenide nanoparticles comprises the following steps of: mixing metal oxide particles(30) and chalcogen material(40) in an organic solvent(20) and stirring the mixed solution; heating the mixed solution up to predetermined temperature in order to chalcogenize the metal oxide particles and obtaining metal chalcogenide nanoparticles; and separating the metal chalcogenide nanoparticles from the mixed solution.
Abstract translation: 目的：提供制备金属硫族化物纳米颗粒的方法和由其制备的金属硫族化物纳米颗粒，以制备各种成型的金属硫族化物纳米颗粒。 构成：制备金属硫族化物纳米颗粒的方法包括以下步骤：将金属氧化物颗粒（30）和硫族元素材料（40）混合在有机溶剂（20）中并搅拌混合溶液; 将混合溶液加热至预定温度，以使金属氧化物颗粒硫化，得到金属硫族化物纳米颗粒; 并从混合溶液中分离金属硫族化物纳米颗粒。
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公开(公告)号：KR100913765B1
公开(公告)日：2009-08-25
申请号：KR1020070096710
申请日：2007-09-21
Applicant: 삼성전기주식회사
IPC: H05K3/46
Abstract: 기판제조방법이 개시된다. 모재와 모재의 일면에 형성된 제1 금속층을 포함하는 지지체를 이용하여 기판을 제조하는 방법으로서, 제1 금속층을 산화시켜 제1 산화금속층을 형성하는 단계; 제1 산화금속층의 일면에 제2 금속층을 형성하는 단계; 제2 금속층의 일면에 회로적층체를 형성하는 단계 및 제1 산화금속층과 제2 금속층을 분리하여 회로적층체를 지지체로부터 분리하는 단계를 포함하는 기판제조방법이 개시된다. 이에 의하면, 모재와 그 일면에 형성된 산화금속층을 포함하는 지지체를 사용하여 회로적층체를 형성하여 그 취출과정을 용이하게 함으로써, 기판제조공정을 단순화시키고 지지체를 구성하는 모재를 재사용함으로써 기판의 제조비용을 절감할 수 있다.
코어리스, coreless, 박형기판
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