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公开(公告)号：KR1020170019807A
公开(公告)日：2017-02-22
申请号：KR1020150114117
申请日：2015-08-12
Applicant: 삼성전자주식회사
CPC classification number: H04L63/0815 , G06F8/61 , G06F21/31 , H04L63/083 , H04L67/1095 , H04W4/00
Abstract: 전자장치가개시된다. 본발명의다양한실시예에따른전자장치는전자장치하우징, 하우징내에위치한메모리, 유저인터페이스, 메모리및 유저인터페이스와전기적으로연결된프로세서를포함하고, 메모리는실행시에프로세서가, 유저인터페이스를통한사용자의로그인요청에응답하여메모리상에적어도하나의어플리케이션을설치하고, 어플리케이션이설치된후 유저인터페이스를통하여사용자의로그아웃요청을수신하고, 로그아웃요청의수신에응답하여어플리케이션과관련된데이터를적어도하나의외부장치로전송하고, 메모리로부터데이터및 어플리케이션의적어도일부를삭제하도록하는인스트럭션들을저장할수 있다. 이외에도명세서를통해파악되는다양한실시예가가능하다.
Abstract translation: 提供一种电子设备和一种通常使用电子设备的方法。 电子设备包括壳体，设置在壳体中的存储器，与至少一个外部设备通信的通信电路，以及与存储器和通信电路电连接的处理器。 所述处理器被配置为响应于来自用户的登录请求来控制在所述存储器上安装至少一个应用，在所述至少一个应用被安装之后从所述用户接收注销请求，发送与所述至少一个应用相关联的数据 使用所述通信电路响应于所述注销请求到所述至少一个外部设备，以及从所述存储器中删除所述至少一个应用的至少一部分和与所述至少一个应用相关联的数据。
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公开(公告)号：KR1020150069868A
公开(公告)日：2015-06-24
申请号：KR1020130156524
申请日：2013-12-16
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76814 , B08B1/002 , B08B3/12 , B08B7/04 , C11D7/06 , C11D7/3245 , C11D7/5004 , C11D11/0047 , H01L21/02065 , H01L21/0337 , H01L21/31058 , H01L21/31144 , H01L21/32139 , H01L21/76877 , H01L27/11582
Abstract: 본발명은유기물세정조성물및 이를이용하는반도체장치의제조방법을제공한다. 이유기물세정조성물은유기막에대한연마공정후의세정공정에적용되며, 수산화물과탈이온수를포함하되, 상기수산화물을 0.01~5 중량%로포함한다.
Abstract translation: 本发明提供了一种有机清洁组合物和使用其的半导体器件的制造方法。 有机清洗组合物适用于在有机薄膜的抛光工艺之后的清洗工艺，其包括氢氧化物和去离子水，其中氢氧化物为0.01-5重量％。
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公开(公告)号：KR1020130088360A
公开(公告)日：2013-08-08
申请号：KR1020120009555
申请日：2012-01-31
Applicant: 삼성전자주식회사 , 동우 화인켐 주식회사
CPC classification number: B23K35/362 , B23K35/3612 , B23K35/3613 , B23K35/3618 , H01L24/11 , H01L2924/12044 , H01L2924/00
Abstract: PURPOSE: A flux composition for solder bumps is provided to have the flux composition in which flux reflow profile and copper corrosion property are excellent, thereby having the excellent bump shape and forming the solder bump in which the defective product is not generated. CONSTITUTION: A flux composition for forming solder bumps includes resin, activator and solvent; and the resin comprises gum rosin and rosin ester; a mass ratio of the gum rosin versus rosin ester is 60:40 ~ 90:10. In addition, a semiconductor device manufacturing method comprises: a step of forming a bump (15) on the substrate (1); a step of providing the flux composition to cover the bump; a step of reflowing the bump; a step of removing a residual flux composition.
Abstract translation: 目的：提供焊锡凸块用助焊剂组合物，其具有焊剂组成，其中焊剂回流曲线和铜腐蚀性能优异，从而具有优异的凸块形状并形成不产生缺陷产物的焊料凸块。 构成：用于形成焊料凸块的焊剂组合物包括树脂，活化剂和溶剂; 树脂包括松香和松香酯; 松香与松香酯的质量比为60:40〜90:10。 此外，半导体器件制造方法包括：在衬底（1）上形成凸块（15）的步骤; 提供焊剂组合物以覆盖凸块的步骤; 回流的一个步骤; 去除残余焊剂组合物的步骤。
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公开(公告)号：KR1020090130701A
公开(公告)日：2009-12-24
申请号：KR1020080056441
申请日：2008-06-16
Applicant: 삼성전자주식회사
Inventor： 강인구
IPC: H01L21/301
CPC classification number: H01L21/78 , H01L21/6836 , H01L23/3171 , H01L24/48 , H01L24/73 , H01L2221/68327 , H01L2224/02166 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/4899 , H01L2224/73265 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
Abstract: PURPOSE: A semiconductor package and a method for manufacturing thereof are provided to suppress a short circuit between a semiconductor chip and a wire by forming an insulating layer beyond the edge of the semiconductor chip. CONSTITUTION: In a device, a semiconductor chip(400) includes a print circuit board, an electrode pad(420) electrically connected to an integrated circuit, and an insulating layer(240) for protecting the integrated circuit. The insulating layer covers the whole top of the semiconductor chip excluding the electrode pad. The insulating layer is extended over the edge of the semiconductor chip. The insulating layer is formed with a polyimide to protect the semiconductor chip from the outside and prevent damage to the integrated circuit. The polyimide is formed in the edge between the electrode pad of the bonding wire and the semiconductor chip. A short circuit between the bonding wire and the semiconductor chip are controlled by the polyimide.
Abstract translation: 目的：提供半导体封装及其制造方法，通过在半导体芯片的边缘之外形成绝缘层来抑制半导体芯片和导线之间的短路。 构成：在器件中，半导体芯片（400）包括印刷电路板，与集成电路电连接的电极焊盘（420）和用于保护集成电路的绝缘层（240）。 绝缘层覆盖除了电极焊盘之外的半导体芯片的整个顶部。 绝缘层在半导体芯片的边缘上延伸。 绝缘层由聚酰亚胺形成，以保护半导体芯片免受外界的影响，并防止对集成电路的损坏。 聚酰亚胺形成在接合线的电极焊盘和半导体芯片之间的边缘。 接合线和半导体芯片之间的短路由聚酰亚胺控制。
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公开(公告)号：KR100574223B1
公开(公告)日：2006-04-27
申请号：KR1020040078790
申请日：2004-10-04
Applicant: 삼성전자주식회사
CPC classification number: H01L25/50 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/1134 , H01L2224/1308 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/78301 , H01L2224/83136 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.
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Patent Agency Ranking
公开(公告)号：KR1020050020501A
公开(公告)日：2005-03-04
申请号：KR1020030058511
申请日：2003-08-23
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H05K3/3452 , H01L2224/10 , H05K3/243 , H05K2201/0989 , H05K2201/10734 , H05K2203/0577 , H05K2203/058
Abstract: PURPOSE: An interconnection board for an NSMD(non solder mask defined)-type BGA(ball grid array) package is provided to avoid a crack in a pattern by reducing concentration of stress on an interface between an interconnection pattern and a solder mask. CONSTITUTION: A body of a board is prepared. An interconnection pattern(70) of a copper material is formed on a surface of the body of the board, including a solder ball pad(72) and a connection pattern(74) connected to the solder ball pad. The first solder mask is formed on a surface of the body of the board, including the first open part(81) to which a part of the solder ball pad and the connection pattern broader than the substantial open part of the solder ball pad is exposed. A plating layer is formed on the solder ball pad and the connection pattern exposed to the first open part. The first solder mask is covered with the second solder mask(84) including the second opening part that corresponds to the substantial open part of the solder ball pad and is narrower than the first open part, wherein a part of the solder ball pad and the connection pattern is exposed to the second open part(83). The interfacial surface of the first open part is protected by the second solder mask.
Abstract translation: 目的：提供用于NSMD（非焊接掩模定义）型BGA（球栅阵列）封装的互连板，以通过减少互连图案和焊接掩模之间的界面上的应力集中来避免图案中的裂纹。 宪法：准备了一个董事会成员。 铜基材的互连图案（70）形成在板的主体的表面上，包括焊球（72）和连接到焊球垫的连接图案（74）。 第一焊料掩模形成在板的主体的表面上，包括第一开口部分（81），焊球的一部分和比焊锡球焊盘的基本开口部分更宽的连接图案暴露在其中 。 在焊锡球焊盘和暴露于第一开放部分的连接图案上形成镀层。 第一焊料掩模被第二焊料掩模（84）覆盖，第二焊料掩模（84）包括对应于焊球垫的基本上开口部分的第二开口部分，并且比第一开口部分窄，其中焊球的一部分和 连接图案暴露于第二开放部分（83）。 第一开口部分的界面由第二焊接掩模保护。
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公开(公告)号：KR100364635B1
公开(公告)日：2002-12-16
申请号：KR1020010006318
申请日：2001-02-09
Applicant: 삼성전자주식회사
IPC: H01L23/02
CPC classification number: H01L24/83 , H01L23/481 , H01L24/29 , H01L24/81 , H01L25/0657 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/8319 , H01L2224/838 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
Abstract: 본발명은칩-레벨 3차원멀티-칩패키지와그 제조방법을제공한다. 본발명에따른멀티-칩패키지는 N개의반도체집적회로소자들이직접적층되어구성되며, 각각의집적회로소자에형성된칩 선택단자들은칩-레벨에형성된 N-1개의칩 선택용패드들을통하여자동으로분리된다. 칩선택용패드들은절연층에형성된금속배선들과관통배선들을통하여상부접속단자들에연결되며, 칩내부를관통하는트렌치배선을통하여하부접속단자들에연결된다. 특히, 칩선택용패드들은이웃하는칩 선택용패드위쪽에있는상부접속단자들에연결되므로, 각각의집적회로소자가접합하여적층을이룰때, 각각의칩 선택단자들은자동으로분리되어맨 아래집적회로소자의하부접속단자들에연결된다.
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公开(公告)号：KR1020020066095A
公开(公告)日：2002-08-14
申请号：KR1020010006318
申请日：2001-02-09
Applicant: 삼성전자주식회사
IPC: H01L23/02
CPC classification number: H01L24/83 , H01L23/481 , H01L24/29 , H01L24/81 , H01L25/0657 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/8319 , H01L2224/838 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
Abstract: PURPOSE: A chip-level three-dimensional multichip package is provided to embody a multichip package not in a package level but in a chip level, by making chip selecting terminals automatically separated through a chip selecting pad formed in an integrated circuit device. CONSTITUTION: One chip selecting terminal(12a) is formed on a chip. (N-1) chip selecting pads are formed on the chip, adjacent to the chip selecting terminal. An insulation layer is formed on the chip. (N-1) metal interconnections are formed inside the insulation layer, connected to the respective chip selecting pads. A plurality of upper connecting terminals(22,22a) are formed on the insulation layer, connected to the respective metal interconnections. A plurality of lower connecting terminals(23,23a,23c) are formed under the chip, corresponding to the chip selecting terminal and the chip selecting pads. A plurality of trench interconnections connect the chip selecting terminal and the chip selecting pads with the respective lower connecting terminals, penetrating the chip. The first chip selecting pad adjacent to the chip selecting terminal is connected to the upper connecting terminal formed over the chip selecting terminal. The (N-1)th chip selecting pad is connected to the upper connecting terminal formed over the (N-2)th chip selecting pad. The upper connecting terminals are attached to the lower connecting terminals to form a stacked layer. The chip selecting terminals formed in the integrated circuit devices(110,120,130,140) are automatically separated and connected from/to the lower connecting terminals located in the lowermost position.
Abstract translation: 目的：提供芯片级三维多芯片封装，以通过使芯片选择端子通过形成在集成电路器件中的芯片选择焊盘自动分离来实现不是封装级而在芯片级的多芯片封装。 构成：芯片上形成一个芯片选择端子（12a）。 （N-1）芯片选择焊盘形成在芯片上，与芯片选择端相邻。 在芯片上形成绝缘层。 （N-1）金属互连形成在绝缘层的内部，连接到各个芯片选择焊盘。 多个上连接端子（22,22a）形成在绝缘层上，连接到相应的金属互连。 多个下连接端子（23,23a，23c）形成在芯片下面，对应于芯片选择端子和芯片选择焊盘。 多个沟槽互连将芯片选择端子和芯片选择焊盘与相应的下连接端子连接，穿透芯片。 与芯片选择端子相邻的第一芯片选择焊盘连接到形成在芯片选择端子上的上连接端子。 第（N-1）个芯片选择焊盘连接到形成在第（N-2）个芯片选择焊盘上的上连接端子。 上连接端子连接到下连接端子以形成堆叠层。 形成在集成电路装置（110,120,130,140）中的芯片选择端子自动地分离并连接到位于最下位置的下连接端子。
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公开(公告)号：KR1020020005935A
公开(公告)日：2002-01-18
申请号：KR1020000039507
申请日：2000-07-11
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/00
Abstract: PURPOSE: A multi-chip package and a method for fabricating the same are provided to prevent a mechanical contact between a processing apparatus and a conductive metal line used for a semiconductor chip and wire bonding. CONSTITUTION: The first semiconductor chip(11) and the second semiconductor chip(13) are adhered to upper faces and lower faces of two rectangular die pads(23a,23b) by using an adhesive(35). Each edge portion of the first semiconductor chip(11) and the second semiconductor chip(13) are supported by the die pads(23a,23b). The die pads(23a,23b) have projected areas(A,B), respectively. Each electrode pad(12,14) of the first semiconductor chip(11) and the second semiconductor chip(13) is connected with an upper face and a lower face of an inner end portion of an inner lead(21) by using conductive metal lines(31,32). A package body(40) is formed by an epoxy molding resin. The epoxy molding resin is filled between first semiconductor chip(11) and the second semiconductor chip(13).
Abstract translation: 目的：提供一种多芯片封装及其制造方法，以防止处理装置与用于半导体芯片的导电金属线和引线接合之间的机械接触。 构成：通过使用粘合剂（35）将第一半导体芯片11和第二半导体芯片13粘接到两个矩形模焊盘（23a，23b）的上表面和下表面。 第一半导体芯片（11）和第二半导体芯片（13）的每个边缘部分由管芯焊盘（23a，23b）支撑。 芯片焊盘（23a，23b）分别具有投影区域（A，B）。 第一半导体芯片（11）和第二半导体芯片（13）的每个电极焊盘（12,14）通过使用导电金属与内部引线（21）的内部端部的上表面和下表面连接 线（31,32）。 包装体（40）由环氧树脂模制树脂形成。 环氧树脂模制树脂填充在第一半导体芯片（11）和第二半导体芯片（13）之间。
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