公开(公告)号：KR1020090118299A

公开(公告)日：2009-11-18

申请号：KR1020080044005

申请日：2008-05-13

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  박일한 ,  심원보

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/2463 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/2436

Abstract: PURPOSE: An AND type flash memory array of a vertical laminate structure, a manufacturing method thereof, and an operating method are provided to perform high integration by forming a local bit line and a local source line in a silicon pin of each layer. CONSTITUTION: An AND type flash memory array of a vertical laminate structure includes one or more bit lines, a local bit line, a memory cell, a local source line, a common source line, a drain selecting line, a source selecting line, and word lines. The local bit line is connected to each bit line(98a,98b,98c) by a first selecting transistor. A plurality of memory cells are parallel connected by using the local bit line as a common drain line. The local source line is commonly connected to a source of each memory cell. The common source line is vertically arranged with each bit line in which the local source line is connected by a second selecting transistor. The drain selecting line and the source selecting line are connected to a gate of the first selecting transistor and a gate of the second selecting transistor. The word lines are connected to a gate of each memory cell.

Abstract translation: 目的：提供垂直层压结构的AND型闪速存储器阵列，其制造方法和操作方法，以通过在每层的硅引脚中形成局部位线和局部源极线来执行高集成度。 构成：垂直层叠结构的AND型闪速存储阵列包括一个或多个位线，局部位线，存储单元，局部源极线，公共源极线，漏极选择线，源选择线和 字线。 局部位线由第一选择晶体管连接到每个位线（98a，98b，98c）。 多个存储单元通过使用本地位线作为公共漏极线并联连接。 本地源线通常连接到每个存储单元的源。 公共源极线垂直地布置有每个位线，其中本地源极线通过第二选择晶体管连接。 漏极选择线和源选择线连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 字线连接到每个存储单元的门。

公开(公告)号：KR1020090118237A

公开(公告)日：2009-11-18

申请号：KR1020080043908

申请日：2008-05-13

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  박상혁

IPC: H01L29/775 ,  H01L21/336

CPC classification number: H01L29/7613 ,  H01L29/4236 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66621

Abstract: PURPOSE: A dual gate single electron transistor having a recess channel and a manufacturing method thereof are provided to reduce whole capacitance of a quantum dot by controlling a junction depth of source/drain. CONSTITUTION: A dual gate single electron transistor having a recess channel includes a substrate, a side gate, a control gate, a source region, a drain region, and a recess channel region. The substrate has a groove shape of a fixed depth. Two side gates(70) are formed in both sides of the groove. A first insulation film(42) is positioned between the two side gates. The control gate(81) is formed on each side gate. A second insulation film(43) is positioned between the control gates. The source region(91) and the drain region(92) are formed on the substrate. The groove is positioned between the source region and the drain region. The recess channel region surrounds the groove in between the source region and the drain region.

Abstract translation: 目的：提供具有凹槽通道的双栅单电子晶体管及其制造方法，以通过控制源极/漏极的结深来减小量子点的整体电容。 构成：具有凹槽的双栅单电子晶体管包括衬底，侧栅极，控制栅极，源极区域，漏极区域和凹陷沟道区域。 基板具有固定深度的凹槽形状。 两个侧门（70）形成在槽的两侧。 第一绝缘膜（42）位于两个侧门之间。 控制门81形成在每个侧门上。 第二绝缘膜（43）位于控制门之间。 源区域（91）和漏极区域（92）形成在基板上。 沟槽位于源极区域和漏极区域之间。 凹槽通道区域围绕源极区域和漏极区域之间的沟槽。

公开(公告)号：KR100800507B1

公开(公告)日：2008-02-04

申请号：KR1020060135357

申请日：2006-12-27

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  강상우

IPC: H01L29/775 ,  H01L21/336

CPC classification number: H01L29/7613 ,  H01L29/4983 ,  H01L29/66439

Abstract: A self-aligned single-electron transistor and a fabricating method thereof are provided to prevent generation of parasitic components of parallel MOSFETs by forming dual gates at both sides centering around a control gate without overlapping therewith. Source and drain regions(22a,24a) are formed on a semiconductor substrate to be separated from each other. A channel region is between the source and drain regions. A control gate(40b) is formed on the channel region. A gate dielectric(70) is formed on an upper portion of the channel region by surrounding the control gate. Two sidewall gates(80a,80b) are formed and self-aligned at both sides of an upper portion of the gate dielectric centering around the control gate. The source and drain regions are self-aligned at each sidewall gate. A dielectric sidewall spacer is formed along each sidewall gate on the source and drain regions.

Abstract translation: 提供自对准单电子晶体管及其制造方法，以通过在不与其重叠的情况下在围绕控制栅极的中心处的两侧形成双栅极来防止并联MOSFET的寄生元件的产生。 源极和漏极区域（22a，24a）形成在半导体衬底上以彼此分离。 沟道区域在源区和漏区之间。 控制栅极（40b）形成在沟道区上。 栅极电介质（70）通过围绕控制栅极而形成在沟道区的上部。 两个侧壁门（80a，80b）在围绕控制栅的中心栅电介质的上部两侧形成并自对准。 源极和漏极区域在每个侧壁栅极处是自对准的。 沿着源极和漏极区域上的每个侧壁栅极形成电介质侧壁间隔物。

公开(公告)号：KR100777016B1

公开(公告)日：2007-11-16

申请号：KR1020060055596

申请日：2006-06-20

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  조성재

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/26513 ,  H01L21/76885 ,  H01L27/11568

Abstract: A NAND flash memory array having a pillar structure and a fabricating method of the same are provided to improve remarkably a degree of integration in comparison with a two-dimensional planar structure by reducing an area of a memory cell in half. One or more insulator strips(24) have a pillar shape protruded in a constant interval on a semiconductor substrate(10). One or more semiconductor strips(14) have a pillar shape protruded in parallel between the insulator strips. One or more trenches(34) are formed by using the insulator strips and the semiconductor strips. Two or three dielectric layers include charge trap layers(44) and are formed at both sidewalls and a bottom of each trench. A sidewall gate(50) is formed on the dielectric layers. A first source/drain region is formed on the semiconductor strip of the bottom of the each trench. A second source/drain region is formed at an upper part of a pillar protruded from each semiconductor strip.

Abstract translation: 提供具有柱结构的NAND快闪存储器阵列及其制造方法，通过将存储单元的面积减少一半，可以显着地提高与二维平面结构相比的集成度。 一个或多个绝缘体条（24）具有在半导体衬底（10）上以恒定间隔突出的柱形。 一个或多个半导体条（14）具有在绝缘体条之间平行突出的柱状。 通过使用绝缘体条和半导体条形成一个或多个沟槽（34）。 两个或三个电介质层包括电荷陷阱层（44），并形成在每个沟槽的两个侧壁和底部。 侧壁栅极（50）形成在电介质层上。 在每个沟槽的底部的半导体条上形成第一源极/漏极区域。 第二源极/漏极区域形成在从每个半导体条突出的柱的上部。

公开(公告)号：KR1020060006163A

公开(公告)日：2006-01-19

申请号：KR1020040055051

申请日：2004-07-15

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  최병용

IPC: H01L29/78

CPC classification number: H01L29/49 ,  H01L21/02142 ,  H01L21/2053 ,  H01L27/1203 ,  H01L2924/13091

Abstract: 본 발명은 전계 효과 트랜지스터의 제조방법에 관한 것으로, 실리콘 및 실리콘 게르마늄 에피텍시(epitaxy) 기술을 적용한 SOI 기판을 이용하여 'T'자형의 게이트 형상을 갖는 소자를 제조함으로써, 종래 'T'자형 게이트 소자의 특성을 그대로 가지면서, 채널은 에피텍시로 얇게 길러진 SOI의 실리콘 에피층을 사용하여 극미세 전계 효과 트랜지스터로 바람직한 완전 공핍형(Fully Depleted Type)의 동작을 만들어 주며, 소스/드레인은 에피텍시로 두껍게 길러진 실리콘 게르마늄 에피층을 이용함으로써 소스/드레인의 시리즈 저항을 줄이고, 나아가 전계 효과 트랜지스터의 채널이 형성될 영역을 형성하기 위한 공정을 개선 함으로써 채널 영역의 실리콘층 두께를 균일성(uniformity)과 재현성(reproducibility) 있게 구현하는 방법을 제공하고 있다.
전계, 효과, 트랜지스터, 측벽, 게르마늄, 에피텍시, SOI

公开(公告)号：KR100483564B1

公开(公告)日：2005-04-15

申请号：KR1020020026415

申请日：2002-05-14

Applicant: 재단법인서울대학교산학협력재단

Inventor： 최병용 ,  이종덕 ,  박병국

IPC: H01L29/78

Abstract: 본 발명은 전계 효과 트랜지스터 및 그의 제조방법에 관한 것으로, SOI((Silicon-On-Insulator)기판을 이용하여, 게이트의 형상을 'T'자형을 갖는 소자를 제조함으로써, 넓은 디자인 창의 게이트 길이(L
1 )를 제공하고, 채널영역에서 바라보는 게이트 길이(L
2 )는 상대적으로 짧아, 극소 채널 형성이 용이하고, 게이트의 지연 및 저항을 줄여 소자의 동작을 빠르게 할 수 있는 효과가 있다.
더불어, 소스와 드레인 영역(3a,3b)의 실리콘층 두께(T
0 )는 채널의 두께(T
2 )보다 두껍게 하여, 저 저항으로 소스/드레인을 동작시킬 수 있는 효과가 발생한다.

公开(公告)号：KR100443754B1

公开(公告)日：2004-08-09

申请号：KR1020020027239

申请日：2002-05-17

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이종덕 ,  최우영

IPC: H01L29/78

Abstract: PURPOSE: A method for manufacturing an FET(Field Effect Transistor) having an LDD(Lightly Doped Drain) is provided to be capable of improving the reproductivity of a process, automating the process, and preventing contamination. CONSTITUTION: After forming the first oxide layer at the upper portion of an isolating layer, the first oxide sidewalls(45a,45b) are formed at both sides of a gate(43a) by carrying out the first dry etching process at the first oxide layer. After forming a nitride layer at the upper portion of the resultant structure, nitride sidewalls are formed at each outer portion of the first oxide sidewalls by carrying out the second dry etching process at the nitride layer. Then, a source and drain region(48a,48b) are formed at a semiconductor substrate(41) by implanting ions. The nitride sidewalls are removed by carrying out the third dry etching process for remaining the first oxide sidewalls alone. At this time, the insulating layer is selectively etched.

Abstract translation: 目的：提供一种用于制造具有LDD（轻掺杂漏极）的FET（场效应晶体管）的方法，以便能够改善过程的再现性，使过程自动化并防止污染。 构成：在隔离层的上部形成第一氧化物层之后，通过在第一氧化物层上进行第一干法刻蚀工艺，在栅极（43a）的两侧形成第一氧化物侧壁（45a，45b） 。 在所得结构的上部形成氮化物层之后，通过在氮化物层处执行第二干蚀刻工艺，在第一氧化物侧壁的每个外部处形成氮化物侧壁。 然后，通过注入离子在半导体衬底（41）上形成源极和漏极区域（48a，48b）。 通过执行第三干蚀刻工艺去除氮化物侧壁，以保留第一氧化物侧壁单独。 此时，绝缘层被选择性地蚀刻。

公开(公告)号：KR1020090058970A

公开(公告)日：2009-06-10

申请号：KR1020070125789

申请日：2007-12-05

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  이동섭

IPC: H01L29/775 ,  H01L29/78

CPC classification number: H01L29/7613 ,  H01L29/66439 ,  H01L29/775

Abstract: A single electron transistor including a constriction barrier and a manufacturing method thereof are provided to implement a tunneling barrier by forming a constriction barrier in an active region in both sides of a control gate. A channel region(12a) is defined as the predetermined micro pattern in a silicon layer(10) of an SOI substrate. A source region(24) and a drain region(26) are separated with a predetermined distance while interposing a channel region. A gate insulating layer is formed in the upper part of the channel region. The gate is formed in the upper part of the gate insulating layer. A channel constriction oxide layer(72) is self-aligned in both sides of the gate. The channel constriction oxide layer encroaches on the channel region.

Abstract translation: 提供包括收缩屏障的单电子晶体管及其制造方法，以通过在控制栅极两侧的有源区域中形成收缩壁垒来实现隧道势垒。 沟道区（12a）被定义为SOI衬底的硅层（10）中的预定微图案。 在插入沟道区域的同时，源区域（24）和漏极区域（26）以预定距离分开。 栅极绝缘层形成在沟道区域的上部。 栅极形成在栅极绝缘层的上部。 通道收缩氧化物层（72）在栅极的两侧自对准。 通道压缩氧化物层侵入通道区域。

公开(公告)号：KR1020080071822A

公开(公告)日：2008-08-05

申请号：KR1020070010165

申请日：2007-01-31

Applicant: 재단법인서울대학교산학협력재단

Inventor： 박병국 ,  송재영

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L29/4236 ,  H01L29/66575 ,  H01L29/785

Abstract: A FIREFET(Fin and Recess channel MOSFET) and a manufacturing method thereof are provided to improve a current driving performance of the FIREFET by reducing source and drain resistances. An active region is surrounded by a field oxide film on a semiconductor substrate. Source/drain(14,16) are formed on the active region with a fin-type channel between them. A recess hole is formed under the source/drain and the fin channel. A recess channel is formed under the fin channel at one side of the recess hole. Gate oxide films(80) are formed on a surface of the recess hole including the recess channel, side surfaces of the source/drain, and the fin channel. A gate(90a) surrounds the recess channel and the fin channel on the gate oxide film and is formed between the recess hole and the source/drain.

Abstract translation: 提供了一种FIREFET（Fin和Recess通道MOSFET）及其制造方法，以通过减少源极和漏极电阻来提高FIREFET的电流驱动性能。 有源区被半导体衬底上的场氧化膜包围。 源极/漏极（14,16）形成在有源区域上，在它们之间具有鳍状沟道。 在源极/漏极和鳍片通道下方形成凹陷孔。 在凹槽的一侧的翅片通道下方形成凹槽。 栅极氧化膜（80）形成在包括凹槽的凹槽的表面上，源/漏和鳍通道的侧表面。 栅极（90a）围绕凹槽通道和栅氧化膜上的散热片通道，并形成在凹槽和源极/漏极之间。

公开(公告)号：KR100724312B1

公开(公告)日：2007-06-04

申请号：KR1020040109058

申请日：2004-12-20

Applicant: 재단법인서울대학교산학협력재단

Inventor： 이종덕 ,  박병국 ,  진성훈 ,  이천안

IPC: H01L29/786

Abstract: 본 발명은 산화막인 게이트 절연막 위에 PMMA 층 또는 증가형 특성을 보이는 게이트 절연막을 도입하여 제조한 p 채널 증가형 소자 및 p 채널 공핍형 소자를 연결하거나, 게이트 절연막으로서 비휘발성 유기 메모리 층을 도입하고 전기적인 프로그래밍에 의하여 음의 문턱전압을 갖는 p 채널 증가형 소자 및 전기적인 프로그래밍에 의하여 양의 문턱전압을 갖는 p 채널 공핍형 소자를 연결한 유기 반도체 회로가 제공된다.
본 발명의 p 채널 증가형 소자와 p 채널 공핍형 소자를 함께 동일 기판 위에 형성하고, 연결하면 풀 스윙이 가능한 반도체 회로를 쉽게 구현할 수 있다.
p 채널, 유기 반도체 회로, 풀 스윙, 증가형 소자, 공핍형 소자, PMMA 층, 게이트 절연막, 유기 메모리, 프로그래밍