公开(公告)号：JP2009153132A

公开(公告)日：2009-07-09

申请号：JP2008322994

申请日：2008-12-18

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： CARVALHO NEVILLE ,  DAVIDSON ALLAN THOMAS ,  TURUDIC ANDY ,  PEDERSEN BRUCE B ,  MENDEL DAVID W ,  KANKIPATI KALYAN ,  ZHENG MICHAEL MENGHUI ,  SHUMARAYEV SERGEY ,  PARK SEUNGMYON ,  HOANG TIM TRI ,  THARMALINGAM KUMARA

IPC: H04L7/033 ,  H03K19/173 ,  H03L7/08 ,  H04L13/08

CPC classification number: H04L25/14

Abstract: PROBLEM TO BE SOLVED: To provide a transceiver system having a reduced latency uncertainty. SOLUTION: The transceiver system has a word aligner with a latency uncertainty of zero. The system also has a bit slipper coupled with the word aligner. The bit slipper slips bits in such a manner that a total delay caused by word alignment of the word aligner and by a bit slip of the bit slipper is constant with respect to all phases of a recovery clock. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供具有减小的等待时间不确定性的收发机系统。

解决方案：收发器系统具有字符对准器，延迟不确定度为零。 该系统还具有与字对准器耦合的位拖鞋。 位拖动器以这样的方式滑动位，使得由字对准器的字对齐引起的总延迟和位拖动器的位滑动相对于恢复时钟的所有相位是恒定的。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009065694A

公开(公告)日：2009-03-26

申请号：JP2008270378

申请日：2008-10-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H01L21/82 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources applied to programmable logic devices for accelerating an operating speed of a programmable logic array integrated circuit device. SOLUTION: A programmable logic integrated circuit (10) has a plurality of regions of programmable logic (20) disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, etc.) are provided for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms having architecturally similar but significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路器件的工作速度。 解决方案：可编程逻辑集成电路（10）具有多个可编程逻辑区域（20），该多个可编程逻辑区域设置在该区域的多个相交行和列的多个设备上。 提供互连资源（例如，互连导体等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以具有架构上相似但显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007097160A

公开(公告)日：2007-04-12

申请号：JP2006240927

申请日：2006-09-06

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LAI TIN ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  WONG WILSON

IPC: H04B3/06

CPC classification number: H03G3/3089 ,  H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To accurately adjust the amount of gain in equalization circuitry. SOLUTION: Equalization circuitry (200) may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages (202) that control the amount of gain provided to the data signal. A comparator (212) may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter (204) may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters (208, 210). The analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry (214) that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：准确调整均衡电路中的增益量。 解决方案：均衡电路（200）可用于补偿由传输介质引起的数据信号的衰减。 用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级（202）的控制输入。 比较器（212）可以确定来自均衡电路的增益是否小于或大于期望的增益量。 可编程上/下计数器（204）可以基于比较器的输出来调整计数器值。 可以使用一个或多个数模转换器（208,210）将计数器值转换成一个或多个模拟电压。 模拟电压可以作为控制输入提供给均衡级。 控制电路还可以包括滞后电路（214），当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP2332258A4

公开(公告)日：2014-02-26

申请号：EP09815015

申请日：2009-09-11

Applicant: ALTERA CORP

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

公开(公告)号：EP2345152A4

公开(公告)日：2013-02-27

申请号：EP09819718

申请日：2009-10-05

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

IPC: H03B5/08 ,  H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

公开(公告)号：EP2553817A4

公开(公告)日：2016-11-16

申请号：EP11759912

申请日：2011-03-15

Applicant: ALTERA CORP

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  ATESOGLU ALI ,  IPPILI SHARAT BABU

IPC: H03L7/099 ,  H01F17/00

CPC classification number: H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

公开(公告)号：EP2561442A4

公开(公告)日：2016-10-19

申请号：EP11772564

申请日：2011-04-19

Applicant: ALTERA CORP

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

公开(公告)号：EP2332304A4

公开(公告)日：2014-07-30

申请号：EP09818103

申请日：2009-09-29

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON

IPC: H04L27/01 ,  H04B3/04 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

公开(公告)号：JP2014099925A

公开(公告)日：2014-05-29

申请号：JP2014030247

申请日：2014-02-20

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/197 ,  H03L7/08 ,  H03L7/199

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To provide a technique for generating a fractional clock signal.SOLUTION: A circuit includes a phase detection circuit, a clock signal generation circuit, a first frequency divider and a second frequency divider. The phase detection circuit compares an input clock signal with a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency-divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency-divided signal. The first and second frequency-divided signals are routed to the phase detection circuit as the feedback signal during different time intervals.

Abstract translation: 要解决的问题：提供一种用于产生分数时钟信号的技术。解决方案：电路包括相位检测电路，时钟信号产生电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以产生控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值，以产生第二分频信号。 在不同的时间间隔期间，第一和第二分频信号作为反馈信号被路由到相位检测电路。

公开(公告)号：JP2014064328A

公开(公告)日：2014-04-10

申请号：JP2013268773

申请日：2013-12-26

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/04

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptive circuit network and a method for a programmable logic device.SOLUTION: A method controls equalization of an incoming data signal. The method comprises steps of: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.

Abstract translation: 要解决的问题：提供数字自适应电路网络和可编程逻辑器件的方法。解决方案：一种控制输入数据信号的均衡的方法。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。