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    41.
    发明专利
    未知

    公开(公告)号：DE10255866B4

    公开(公告)日：2006-11-23

    申请号：DE10255866

    申请日：2002-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LUETZEN JOERN ,  BIRNER ALBERT ,  KUDELKA STEPHAN ,  TEWS HELMUT ,  WEIS ROLF

    IPC: H01L21/306 ,  H01L27/108 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8242 ,  H01L29/04

    Abstract: A process for increasing the structural density (thickness, sic) and/or storage capacity of structures introduced into a semiconductor wafer (1) by marking (2) in the rupture direction, where the structures by means of a light exposure device and a mask (3) are formed on the wafer. Before formation of the structures the wafer is turned by 45 deg in its plane and is given a marking in a new direction parallel to a (100) crystal orientation. A process for increasing the structural size (density, sic) of main structures (MS) formed in the bulk of a SS by an etching process, in which main structures on one surface of the SS are exchanged in a surface section of the SS by secondary structures arranged in a surface screen (14) and directed with longitudinal and transverse extension parallel to the x and y axes of the surface screen where before etching the longitudinal and transverse extensions of the main structures are twisted relative to the x and y axes of surface screen so that the section of the SS below the secondary MS main structures is made completely available for formation of further MS by means of a further etching process. Independent claims are included for: (1) a structure in a SS comprising a drain with a limiting upper section at the surface of the SS of plan view surface profile with longitudinal sides parallel to the (100) crystal orientation and with rectangular profile in a lower section below an etch resistant protective layer with longitudinal sides parallel to the (110) crystal orientation; (2) an arrangement of structures in which the thickness of the intermediate walls between adjacent structures in the SS is of the order of 100 nm; (3) a process for reduction of leakage current in a selection transistor and a DRAM-cell with storage capacity, where DRAM = dynamic random access memory, with processing of a semiconductor wafer having a DRAM-cell; (4) a DRAM-cell obtained as above and having storage capacity.

    42.
    发明专利
    未知

    公开(公告)号：DE10348006B4

    公开(公告)日：2006-07-20

    申请号：DE10348006

    申请日：2003-10-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

    47.
    发明专利
    未知

    公开(公告)号：DE102004033825B4

    公开(公告)日：2009-05-14

    申请号：DE102004033825

    申请日：2004-07-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEWS HELMUT ,  BARTH HANS-JOACHIM

    IPC: H01L21/822 ,  H01L21/02 ,  H01L21/768 ,  H01L27/08

    Abstract: The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.

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