公开(公告)号：HK1046045B

公开(公告)日：2008-12-19

申请号：HK02107457

申请日：2002-10-15

Applicant: INTEL CORP

Inventor： RODGERS DION ,  TOLL BRET ,  WOOD AMIEE

IPC: G06F20060101 ,  G06F15/00 ,  G06F9/38

公开(公告)号：DE102007037814A1

公开(公告)日：2008-03-27

申请号：DE102007037814

申请日：2007-08-10

Applicant: INTEL CORP

Inventor： BENNET STEVEN M ,  ANDERSON ANDREW V ,  NEIGER GILBERT ,  UHLIG RICHARD ,  RODGERS DION ,  MADUKKARUMUKUMANA RAJESH ,  RUST CAMRON ,  SCHOENBERG SEBASTIAN

IPC: G06F12/06

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：DE112005002360T5

公开(公告)日：2007-08-23

申请号：DE112005002360

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  BENNETT STEVEN ,  COTA-ROBLES ERIK ,  SCHOENBERG SEBASTIAN ,  HALL CLIFFORD ,  RODGERS DION ,  SMITH LAWRENCE ,  ANDERSON ANDREW ,  UHLIG RICHARD ,  KOZUCH MICHAEL ,  GLEW ANDY

IPC: G06F9/455

Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.

公开(公告)号：DE102006039747A1

公开(公告)日：2007-03-29

申请号：DE102006039747

申请日：2006-08-24

Applicant: INTEL CORP

Inventor： NEWBURN CHRIS ,  RODGERS DION ,  BIGBEE BRYANT ,  KAUSHIK SHIVNANDAN ,  CHINYA GAUTHAM ,  ZOU XIANG ,  WANG HONG

IPC: G06F9/00

Abstract: The device has a saving region (100) and a head region (105). The saving region is provided with a set of segments for storing processor context state information, where the context state information is stored in each of the set of segments. The context state information is restored to a processor context state independent of other context state information that is stored in other segments. Independent claims are also included for the following: (1) a method for context state management (2) a computer system comprising a processor (3) a processor comprising channel information.

公开(公告)号：DE102005034675A1

公开(公告)日：2006-03-23

申请号：DE102005034675

申请日：2005-07-25

Applicant: INTEL CORP

Inventor： FISCHER STEPHEN ,  RODGERS DION ,  SUTTON II JAMES

IPC: G06F9/00 ,  G06F9/44

Abstract: A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.

公开(公告)号：DE60109748D1

公开(公告)日：2005-05-04

申请号：DE60109748

申请日：2001-01-17

Applicant: INTEL CORP

Inventor： MARR T ,  RODGERS DION

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

公开(公告)号：DE102004030034A1

公开(公告)日：2005-01-27

申请号：DE102004030034

申请日：2004-06-22

Applicant: INTEL CORP

Inventor： COKE JAMES ,  RUSCITO PETER ,  TAHIR MASOOD ,  JACKSON DAVID ,  NAYDENOV VES ,  RODGERS DION ,  TOLL BRET ,  BINNS FRANK

IPC: G06F9/30 ,  G06F9/00 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

公开(公告)号：HK1046460A1

公开(公告)日：2003-01-10

申请号：HK02108030

申请日：2002-11-05

Applicant: INTEL CORP

Inventor： RODGERS DION ,  BOGGS DARRELL ,  MERCHANT AMIT ,  KOTA RAJESH ,  HSU RACHEL

IPC: G06F20060101 ,  G06F9/46 ,  G06F9/318 ,  G06F9/38

Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

公开(公告)号：AU8021100A

公开(公告)日：2001-06-18

申请号：AU8021100

申请日：2000-10-12

Applicant: INTEL CORP

Inventor： RODGERS DION ,  BOGGS DARRELL ,  MERCHANT AMIT ,  KOTA RAJESH ,  HSU RACHEL ,  TIRUVALLUR KESHAVAN

IPC: G06F9/38

Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

公开(公告)号：AU8015100A

公开(公告)日：2001-06-18

申请号：AU8015100

申请日：2000-10-11

Applicant: INTEL CORP

Inventor： RODGERS DION ,  TOLL BRET ,  WOOD AMIEE

IPC: G06F15/00 ,  G06F9/38

Abstract: A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.