公开(公告)号：CA3031207C

公开(公告)日：2021-12-28

申请号：CA3031207

申请日：2017-07-17

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  ZUO CHENGJIE ,  FANELLI STEVE ,  MASARACIOGLU HUSNU AHMET

IPC: H01L23/31 ,  H01L21/60 ,  H01L23/538

Abstract: A package (300) includes a redistribution portion (302), a first portion (204), and a second portion (206). The first portion is coupled to the redistribution portion. The first portion includes a first switch (241) comprising a plurality of switch interconnects (245), and a first encapsulation layer (240) that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters (261). Each filter includes a plurality of filter interconnects (265). The second portion also includes a second encapsulation layer (260) that at least partially encapsulates the first plurality of filters. The first portion includes a second switch (243) positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters (263) positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters.

公开(公告)号：CA3007083A1

公开(公告)日：2017-07-20

申请号：CA3007083

申请日：2016-11-29

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  ZUO CHENGJIE ,  FANELLI STEVE ,  GEE THOMAS ,  SONG YOUNG KYU

IPC: H01L23/66 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

公开(公告)号：CA2991933A1

公开(公告)日：2017-03-02

申请号：CA2991933

申请日：2016-06-03

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  WE HONG BOK ,  LEE JAE SIK ,  KIM DONG WOOK

IPC: H01L23/538

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

公开(公告)号：CA2720966C

公开(公告)日：2015-06-30

申请号：CA2720966

申请日：2009-04-27

Applicant: QUALCOMM INC

Inventor： KASKOUN KENNETH ,  GU SHIQUN ,  NOWAK MATTHEW M

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/373

Abstract: By filling an air gap between tiers (31,32) of a stacked IC device with a thermally conductive material (320) heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal materia can be electrically insulating. Through silicon-vias (331) can be constructe at certain locations to assist in heat dissipation away from thermally troubled locations (310).

公开(公告)号：CA2711305C

公开(公告)日：2015-02-10

申请号：CA2711305

申请日：2009-01-08

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  KANG SEUNG H ,  NORWAK MATTHEW M

IPC: H01L43/08

Abstract: A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.

公开(公告)号：MX2010011848A

公开(公告)日：2010-11-30

申请号：MX2010011848

申请日：2009-04-27

Applicant: QUALCOMM INC

Inventor： GU SHIQUN ,  KASKOUN KENNETH ,  NOWAK MATTHEW M

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/373

Abstract: Mediante el relleno de un espacio de aire entre las capas (31,32) de un dispositivo IC apilado con un material térmicamente conductor (320), se puede desplazar lateralmente el calor generado en una o más ubicaciones dentro de una de las capas. El desplazamiento lateral del calor puede ser a lo largo de la longitud total de la capa y el material térmico se puede aislar eléctricamente. En ciertas ubicaciones se pueden construir interconexiones de silicio continuas (331) para ayudar en la disipación de calor lejos de las ubicaciones (310) con problemas térmicos.

公开(公告)号：MX2010006977A

公开(公告)日：2010-09-10

申请号：MX2010006977

申请日：2008-12-19

Applicant: QUALCOMM INC

Inventor： KANG SEUNG H ,  ZHU XIAOCHUN ,  GU SHIQUN ,  LI XIA

IPC: G11C11/16

Abstract: En una modalidad, se describe un dispositivo que incluye una estructura e unión magnética en forma de túnel (MTJ). El dispositivo también incluye una vía (102) de lectura acoplada con la estructura MTJ y una vía (104) de escritura acoplada con la estructura MTJ. La vía (104) de escritura se encuentra separada de la vía (102) de lectura. En esencia, el dispositivo comprende un par de estructuras (106, 108) MTJ acopladas en serie, por medio de las cuales, la vía de lectura sólo comprende una estructura (108) MTJ. Esto proporciona un margen de lectura mejorado y un margen de escritura mejorado en combinación.

公开(公告)号：CA2735689A1

公开(公告)日：2010-03-18

申请号：CA2735689

申请日：2009-09-01

Applicant: QUALCOMM INC

Inventor： KASKOUN KENNETH ,  GU SHIQUN ,  NOWAK MATTHEW

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/60

Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.

公开(公告)号：WO2012027423A3

公开(公告)日：2012-04-26

申请号：PCT/US2011048885

申请日：2011-08-24

Applicant: QUALCOMM INC ,  GU SHIQUN ,  NOWAK MATTHEW M ,  SRINIVASAN ANAND

Inventor： GU SHIQUN ,  NOWAK MATTHEW M ,  SRINIVASAN ANAND

IPC: H01L23/48 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.

Abstract translation: 具有高密度，高延迟内存块的外部存储器; 和一个低密度，低延迟的存储块。 两个存储块可以由一个或多个处理功能单元分开访问。 访问可以是直接内存访问，也可以是总线或光纤交换机。 直通管芯过孔可以将外部存储器连接到包括一个或多个处理功能单元的管芯。

公开(公告)号：WO2012135832A2

公开(公告)日：2012-10-04

申请号：PCT/US2012031861

申请日：2012-04-02

Applicant: QUALCOMM INC ,  GU SHIQUN ,  RADOJCIC RATIBOR ,  LI YIMING

Inventor： GU SHIQUN ,  RADOJCIC RATIBOR ,  LI YIMING

IPC: H01L23/60

CPC classification number: H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

Abstract translation: 可以在用于静电放电（ESD）保护的管芯上采用电压可切换介电层。 在模具的正常操作期间，电压可切换介电层用作裸片的端子之间的介电层。 当ESD事件发生在管芯的端子处时，端子之间的高电压将电压可切换介电层切换为导电层，以允许电流放电至管芯的接地端子，而电流不通过管芯的电路。 因此，在具有电压可切换电介质层的管芯上的ESD事件期间，减小或防止了管芯电路的损坏。 可以在用第二管芯堆叠期间将电压可切换介电层沉积在管芯的背侧以用于保护以形成堆叠式IC。