公开(公告)号：ITMI20012284A1

公开(公告)日：2003-04-30

申请号：ITMI20012284

申请日：2001-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGRI ANGELO

IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

Abstract: The invention relates to an electronic power device (1) of improved structure and fabricated with MOS technology to have at least one gate finger region (3) and corresponding source regions (4) on opposite sides of the gate region (3). This device (1) has at least one first-level metal layer (3',4') arranged to independently contact the gate region (3) and source regions, and has a protective passivation layer (5) arranged to cover the gate region (3). Advantageously, a wettable metal layer (7), deposited onto the passivation layer (5) and the first-level metal layer (4'), overlies said source regions (4). In this way, the additional wettable metal layer (7) is made to act as a second-level metal.

公开(公告)号：DE69429915D1

公开(公告)日：2002-03-28

申请号：DE69429915

申请日：1994-07-04

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

公开(公告)号：ITMI20112273A1

公开(公告)日：2013-06-16

申请号：ITMI20112273

申请日：2011-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： ABBONDANZA GIUSEPPE ,  FRISINA FERRUCCIO

公开(公告)号：DE69534919T2

公开(公告)日：2007-01-25

申请号：DE69534919

申请日：1995-10-30

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

IPC: H01L29/06 ,  H01L29/74 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: A MOS technology power device comprises: a semiconductor material layer (2) of a first conductivity type; a conductive insulated gate layer (7,8,9) covering the semiconductor material layer (2); a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a second conductivity type formed in the semiconductor material layer (2), the body region (3) having the form of an elongated body stripe, each elementary functional unit further comprising an elongated window (12) in the insulated gate layer (7,8,9) extending above the elongated body stripe (3). Each body stripe (3) includes at least one source portion (60;61;62) doped with dopants of the first conductivity type, intercalated with a body portion (40;41;3') of the body stripe (3) wherein no dopant of the first conductivity type are provided. The conductive insulated gate layer (7,8,9) comprises a first insulating material layer (7) placed above the semiconductor material layer (2), a conductive material layer (8) placed above the first insulating material layer (7), and a second insulating material layer (9) placed above the conductive material layer (8). Insulating material sidewall spacers (13) are provided to seal edges of the elongated window (12) in the insulated gate layer (7,8,9).

公开(公告)号：DE69434268D1

公开(公告)日：2005-03-17

申请号：DE69434268

申请日：1994-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

公开(公告)号：ITMI20022700A1

公开(公告)日：2004-06-21

申请号：ITMI20022700

申请日：2002-12-20

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  SAGGIO MARIO

IPC: H01L20060101 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78

公开(公告)号：DE69428894T2

公开(公告)日：2002-04-25

申请号：DE69428894

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/739

Abstract: A power device integrated structure comprises a semiconductor substrate (5) of a first conductivity type, a semiconductor layer (3,4) of a second conductivity type superimposed over said substrate (5), a plurality of first doped regions (2) of the first conductivity type formed in the semiconductor layer (3,4), and a respective plurality of second doped regions (11) of the second conductivity type formed inside the first doped regions (2); the power device comprises: a power MOSFET (M) having a first electrode region represented by the second doped regions (11) and a second electrode region represented by the semiconductor layer (3,4); a first bipolar junction transistor (T2) having an emitter, a base and a collector respectively represented by the substrate (5), the semiconductor layer (3,4) and the first doped regions (2); and a second bipolar junction transistor (T1) having an emitter, a base and a collector respectively represented by the second doped regions (11), the first doped regions (2) and the semiconductor layer (3,4); the doping profiles of the semiconductor substrate (5), the semiconductor layer (3,4), the first doped regions (2) and the second doped regions (11) are such that the first and second bipolar junction transistors (T2,T1) have respective first and second common base current gains sufficiently high to cause said bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate (5) into the semiconductor layer (3,4) and from the second doped regions (11), through the first doped regions (2), into the semiconductor layer (3,4), the conductivity of the semiconductor layer (3,4) is thus modulated not only by the injection of minority carriers from the substrate (5), but also by majority carriers injected from the doped regions (11) into the first doped regions (2) and collected by the semiconductor layer (3,4). The first and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on. The power device functions as an IGBT, having a reduced on-state voltage.

公开(公告)号：DE69839439D1

公开(公告)日：2008-06-19

申请号：DE69839439

申请日：1998-05-26

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI' ANGELO ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739

Abstract: High density MOS technology power device structure, comprising body regions (31A-31D) of a first conductivity type formed in a semiconductor layer (1) of a second conductivity type, characterized in that said body regions comprise at least one plurality of substantially rectilinear and substantially parallel body stripes (32) each joined at its ends to adjacent body stripes (32) by means of junction regions (33), so that said at least one plurality of body stripes (32) and said junction regions (33) form a continuous, serpentine-shaped body region (31A-31D).

公开(公告)号：DE69434268T2

公开(公告)日：2006-01-12

申请号：DE69434268

申请日：1994-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: A high-speed MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a lightly doped semiconductor layer (1) of a first conductivity type, the elementary functional units comprising channel regions (6) of a second conductivity type covered by a conductive insulated gate layer (8) comprising a polysilicon layer (5); the conductive insulated gate layer (8) also comprises a highly conductive layer (9) superimposed over said polysilicon (5) layer and having a resistivity much lower than the resistivity of the polysilicon layer (5), so that a resistance introduced by the polysilicon layer (5) is shunted with a resistance introduced by said highly conductive layer (9) and the overall resistivity of the conductive insulated gate (8) layer is lowered.

公开(公告)号：DE60112726D1

公开(公告)日：2005-09-22

申请号：DE60112726

申请日：2001-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： COFFA SALVATORE ,  LIBERTINO SEBANIA ,  FRISINA FERRUCCIO

IPC: H01L31/0288 ,  H01L31/107

Abstract: The high-gain photodetector (1) is formed in a semiconductor-material body (5) which houses a PN junction (13, 14) and a sensitive region (19) that is doped with rare earths, for example erbium (Er). The PN junction (13, 14) forms an acceleration and gain region (13, 14) separate from the sensitive region (19). The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region (19). Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction (13-14), which is transparent to light, can be captured by an erbium ion in the sensitive region (19), so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.