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    ELECTRON BEAM PROCESSING WITH CONDENSED ICE
    42.
    发明申请
    ELECTRON BEAM PROCESSING WITH CONDENSED ICE 审中-公开
    电子束加工与冷凝冰

    公开(公告)号：WO2012099635A3

    公开(公告)日：2012-12-27

    申请号：PCT/US2011057805

    申请日：2011-10-26

    Applicant: HARVARD COLLEGE ,  BRANTON DANIEL ,  HAN ANPAN ,  GOLOVCHENKO JENE A

    Inventor： BRANTON DANIEL ,  HAN ANPAN ,  GOLOVCHENKO JENE A

    IPC: H01L21/027

    CPC classification number: G03F7/2059 ,  B81C1/00531 ,  B81C2201/0143 ,  B81C2201/0159 ,  B82Y10/00 ,  B82Y40/00 ,  G01N23/2251 ,  H01J37/3174 ,  H01J2237/004 ,  H01J2237/022 ,  H01J2237/2002 ,  H01J2237/2803 ,  H01J2237/2809 ,  H01J2237/31796 ,  H01L21/0331 ,  H01L22/12 ,  H01L51/0014 ,  H01L51/0048

    Abstract: In a method for imaging a solid state substrate, a vapor is condensed to an amorphous solid water condensate layer on a surface of a solid state substrate. Then an image of at least a portion of the substrate surface is produced by scanning an electron beam along the substrate surface through the water condensate layer. The water condensate layer integrity is maintained during electron beam scanning to prevent electron-beam contamination from reaching the substrate during electron beam scanning. Then one or more regions of the layer can be locally removed by directing an electron beam at the regions. A material layer can be deposited on top of the water condensate layer and any substrate surface exposed at the one or more regions, and the water condensate layer and regions of the material layer on top of the layer can be removed, leaving a patterned material layer on the substrate.

    Abstract translation: 在用于使固态衬底成像的方法中，蒸汽被冷凝成固态衬底表面上的无定形固体水凝聚物层。 然后通过水冷凝层沿基板表面扫描电子束产生至少一部分基板表面的图像。 在电子束扫描期间保持凝结水层的完整性，以防止在电子束扫描期间电子束污染物到达衬底。 然后可以通过在这些区域处引导电子束来局部去除该层的一个或多个区域。 材料层可以沉积在水冷凝层和在一个或多个区域处暴露的任何基底表面的顶部，并且可以去除层的顶部上的水凝结物层和材料层的区域，留下图案化的材料层 在衬底上。

    MONOLITHIC THREE-DIMENSIONAL STRUCTURES
    45.
    发明申请
    MONOLITHIC THREE-DIMENSIONAL STRUCTURES 审中-公开
    单片三维结构

    公开(公告)号：WO2003025981A1

    公开(公告)日：2003-03-27

    申请号：PCT/US2002/019817

    申请日：2002-07-15

    Applicant: BINOPTICS CORPORATION

    Inventor： BEHFAR, Alex ,  SCHREMER, Alfred, T. ,  STAGARESCU, Cristian, B.

    IPC: H01L21/00

    CPC classification number: G02B6/12002 ,  B81B2201/047 ,  B81C99/008 ,  B81C2201/0159 ,  G02B6/13 ,  G02B6/4204 ,  G02B6/4249 ,  G03F7/0037 ,  Y10S438/948 ,  Y10S438/949 ,  Y10S438/95

    Abstract: Three-dimensional structures of arbitrary shape are fabricated on the surface of a substrate (10) through a series of processing steps wherein a monolithic structure is fabricated in successive layers. A first layer (14) of photoresist material is spun onto a substrate (10) surface (18) and is exposed (26) in a desired pattern corresponding to the shape of a final structure, at a corresponding cross-sectional level in the structure. The layer is not developed after exposure; instead, a second layer (30) of photoresist material is deposited and is also exposed (32) in a desired pattern. Subsequent layers (40,52,64) spun onto the top surface of prior layers (14,30) and exposed (44,54,66), and upon completion of the succession of layers each defining corresponding levels of the desired structure, the layers are all developed at the same time leaving the three-dimensional structure (22).

    Abstract translation: 通过一系列处理步骤在基片（10）的表面上制造任意形状的三维结构，其中单片结构以连续的层制造。 将光致抗蚀剂材料的第一层（14）旋涂到基材（10）表面（18）上，并以对应于最终结构形状的所需图案以结构中相应的横截面水平曝光（26） 。 暴露后层不发达; 替代地，沉积光致抗蚀剂材料的第二层（30）并且还以期望的图案暴露（32）。 随后的层（40,52,64）旋转到先前层（14,30）的顶表面并暴露（44,54,66），并且在各层完成后，各层限定所需结构的相应水平， 所有层都同时开发出离开三维结构（22）。

    PROCESS FOR INTEGRATING DIELECTRIC OPTICAL COATINGS INTO MICROELECTROMECHANICAL DEVICES
    46.
    发明申请
    PROCESS FOR INTEGRATING DIELECTRIC OPTICAL COATINGS INTO MICROELECTROMECHANICAL DEVICES 审中-公开
    将介电光学涂层集成到微电子设备中的方法

    公开(公告)号：WO02033458A2

    公开(公告)日：2002-04-25

    申请号：PCT/US2001/032512

    申请日：2001-10-17

    IPC: B81B3/00 ,  G02B26/00 ,  G02B6/00

    CPC classification number: B81B3/0083 ,  B81B2201/042 ,  B81B2201/047 ,  B81C1/0038 ,  B81C2201/0159 ,  B81C2201/053 ,  B81C2201/056 ,  G02B26/001

    Abstract: A process for patterning dielectric layers of the type typically found in optical coatings in the context of MEMS manufacturing is disclosed. A dielectric coating is deposited over a device layer, which has or will be released, and patterned using a mask layer. In one example, the coating is etched using the mask layer as a protection layer. In another example, a lift-off process is shown. The primary advantage of photolithographic patterning of the dielectric layers in optical MEMS devices is that higher levels of consistency can be achieved in fabrication, such as size, location, and residual material stress. Competing techniques such as shadow masking yield lower quality features and are difficult to align. Further, the minimum feature size that can be obtained with shadow masks is limited to SIMILAR 100 mu m, depending on the coating system geometry, and they require hard contact with the surface of the wafer.

    Abstract translation: 公开了一种用于在MEMS制造的上下文中通常在光学涂层中发现的类型的介电层图案的工艺。 电介质涂层沉积在器件层上，器件层已经或将被释放，并使用掩模层进行图案化。 在一个实例中，使用掩模层作为保护层来蚀刻涂层。 在另一示例中，示出了剥离过程。 光学MEMS器件中电介质层的光刻图案的主要优点是可以在诸如尺寸，位置和残余材料应力的制造中实现更高水平的稠度。 诸如阴影掩蔽的竞争技术产生较低的质量特征并且难以对准。 此外，根据涂层系统的几何形状，使用荫罩可获得的最小特征尺寸限制为100微米，并且它们需要与晶片的表面硬接触。

    INTEGRATED CAPACITIVE HUMIDITY SENSOR
    47.
    发明公开
    INTEGRATED CAPACITIVE HUMIDITY SENSOR 审中-公开
    集成电容式湿度传感器

    公开(公告)号：EP3211409A1

    公开(公告)日：2017-08-30

    申请号：EP17154932.2

    申请日：2017-02-07

    Applicant: NXP USA, Inc.

    Inventor： ZHANG, Qing ,  CHOUDHURI, Mohommad Mahbub ,  ZEB, Gui

    IPC: G01N27/22

    CPC classification number: B81B7/008 ,  B81B2201/0214 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/0159 ,  B81C2201/016 ,  B81C2201/019 ,  G01N27/223

    Abstract: A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

    Abstract translation: 一种由电容式湿度传感器构成的半导体器件，该电容式湿度传感器包括电接枝到位于CMOS衬底或组合的MEMS和CMOS衬底上的导电金属层并且通过钝化层暴露于开口内的湿敏聚合物层， 封装的器件以及在半导体器件内形成电容式湿度传感器的方法。

    A METHOD OF MANUFACTURING A PLURALITY OF THROUGH-HOLES IN A LAYER
    48.
    发明公开
    A METHOD OF MANUFACTURING A PLURALITY OF THROUGH-HOLES IN A LAYER 审中-公开
    一种在一层中制造多个通孔的方法

    公开(公告)号：EP3210937A1

    公开(公告)日：2017-08-30

    申请号：EP17158214.1

    申请日：2017-02-27

    Applicant: SmartTip B.V.

    Inventor： SARAJLIC, Edin

    IPC: B81C1/00 ,  A61B5/15

    CPC classification number: B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

    Abstract: A method of manufacturing a plurality of through-holes (132) in a layer of first material, for example for the manufacturing of a probe (100) comprising a tip containing a channel. To manufacture the through-holes (132) in a batch process,
    - a layer of first material is deposited on a wafer (200) comprising a plurality of pits (210)
    - a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits (210);
    - using the second layer as a shadow mask when depositing a third layer (240) at an angle, covering a part of the first material with said third material (240) at the central locations, and
    - etching the exposed parts of the first layer using the third layer (240) as a protective layer.

    Abstract translation: 一种在第一材料层中制造多个通孔（132）的方法，例如用于制造包括包含通道的尖端的探针（100）。 为了以间歇工艺制造通孔（132）， - 在包括多个凹坑（210）的晶片（200）上沉积第一材料层 - 在第一材料层上提供第二层，以及 第二层在凹坑（210）的中心位置设置有多个孔; - 当以一定角度沉积第三层（240）时，使用第二层作为阴影掩模，在中心位置处用所述第三材料（240）覆盖第一材料的一部分，以及 - 蚀刻第一层 使用第三层（240）作为保护层。

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