公开(公告)号：KR1020160014195A

公开(公告)日：2016-02-11

申请号：KR1020140095943

申请日：2014-07-28

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  백재직 ,  송명근 ,  윤보언 ,  최석헌 ,  한정남

IPC: H01L29/78 ,  H01L21/335

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7811

Abstract: 본발명은반도체장치및 이의제조방법에관한것으로, 보다구체적으로, 활성패턴이제공된기판; 상기활성패턴을가로지르는게이트전극; 및상기게이트전극상의게이트캡핑패턴을포함할수 있다. 이때, 상기게이트캡핑패턴의폭은상기게이트전극의폭보다크고, 상기게이트캡핑패턴은, 상기게이트전극의양 측벽들을덮으며상기기판을향하여연장된연장부를포함할수 있다.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括：衬底，其包括有源图案; 穿过有源图案的栅电极; 和栅极电极上的栅极覆盖图案。 此时，栅极覆盖图案的宽度比栅电极的宽度宽，并且栅极封盖图案包括覆盖栅电极的两个侧壁并朝向衬底延伸的延伸部分。 因此，半导体器件包括具有更好的电性能的场效应晶体管。

公开(公告)号：KR1020150077543A

公开(公告)日：2015-07-08

申请号：KR1020130165535

申请日：2013-12-27

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  전하영 ,  조병권 ,  한정남

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: 대체금속게이트전극의높이변화를경감시켜동작성능을향상시킬수 있는반도체장치를제공하는것이다. 상기반도체장치는트렌치를정의하고, 기판상에순차적으로위치하는제1 부분과제2 부분을포함하는게이트스페이서로, 상기제1 부분의내측면은예각인기울기를갖고, 상기제2 부분의내측면은직각또는둔각인기울기를갖는게이트스페이서, 및상기트렌치의적어도일부를채우는게이트전극을포함한다.

Abstract translation: 本发明提供一种半导体器件，其可以通过减少替代金属栅电极的高度的变化来提高操作性能。 半导体器件包括：栅极间隔物，其限定沟槽并且包括依次位于衬底上的第一部分和第二部分，其中第一部分的内表面具有锐角，并且第二部分的内表面具有 直角或钝角; 以及填充沟槽的至少一部分的栅电极。

公开(公告)号：KR1020150019853A

公开(公告)日：2015-02-25

申请号：KR1020130097254

申请日：2013-08-16

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  윤영상 ,  한정남 ,  권기상 ,  윤두성 ,  조병권 ,  차지훈

IPC: H01L21/31 ,  H01L21/3205

CPC classification number: H01L29/66477 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Provided is a method for forming a trench of a semiconductor device. The method for forming a trench of a semiconductor device includes: a step of forming a trench in an oxide film; a step of forming, in a conformal way, a first reaction film along the surface of the trench, in which the first reaction film includes a first area placed in an upper part of the trench and a second area placed in a lower part of the trench; a step of forming a barrier film by reacting a first amount of etching gas to the first area of the first reaction film; and a step of etching the oxide film placed in a lower part of the second area by reacting a second amount of etching gas, which is more than the first amount, to the second area of the first reaction film.

Abstract translation: 提供一种形成半导体器件的沟槽的方法。 形成半导体器件的沟槽的方法包括：在氧化膜中形成沟槽的步骤; 沿着保形方式形成沿着沟槽表面的第一反应膜的步骤，其中第一反应膜包括放置在沟槽的上部的第一区域和放置在沟槽的下部的第二区域 沟; 通过使第一量的蚀刻气体与第一反应膜的第一区域反应形成阻挡膜的步骤; 以及通过使超过第一量的第二量的蚀刻气体与第一反应膜的第二区域反应来蚀刻放置在第二区域的下部的氧化膜的步骤。

公开(公告)号：KR1020140101505A

公开(公告)日：2014-08-20

申请号：KR1020130014656

申请日：2013-02-08

Applicant: 삼성전자주식회사

Inventor： 윤영상 ,  송명근 ,  차지훈 ,  백재직 ,  윤보언 ,  한정남

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L21/2652 ,  H01L21/763 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device comprises a step of forming a plurality of fins by forming a plurality of first device isolation trenches repeated with a first pitch on a substrate; a step of forming a first device isolation film within the first device isolation trenches and defining a plurality of fin-type active regions protruding from the upper surface of the first device isolation film; and a step of forming a plurality of second device isolation trenches repeated with a second pitch different from the first pitch on the substrate by etching a portion of the first device isolation film and the substrate, forming a second device isolation film within the second device isolation trenches, and forming a plurality of fin-type active region groups spaced apart from each other across the second device isolation film.

Abstract translation: 制造半导体器件的方法包括通过在衬底上以第一间距重复形成多个第一器件隔离沟槽来形成多个鳍的步骤; 在第一器件隔离沟槽内形成第一器件隔离膜并限定从第一器件隔离膜的上表面突出的多个鳍式有源区; 以及通过蚀刻所述第一器件隔离膜和所述衬底的一部分，在所述衬底上以与所述第一间距不同的第二间距重复形成多个第二器件隔离沟槽的步骤，在所述第二器件隔离中形成第二器件隔离膜 并且形成跨越第二器件隔离膜彼此间隔开的多个翅片型有源区域组。

公开(公告)号：KR1020140094722A

公开(公告)日：2014-07-31

申请号：KR1020130006603

申请日：2013-01-21

Applicant: 삼성전자주식회사

Inventor： 차지훈 ,  백재직 ,  윤보언 ,  윤영상 ,  한정남

IPC: H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66628 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/66477 ,  H01L21/8238 ,  H01L29/7802 ,  H01L29/7804

Abstract: Provided is a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes exposing an active region and a device isolation region by patterning an etch prevention layer which is formed on a substrate which includes the active region and the device isolation region; nitrifying the upper surface of the exposed device isolation region by performing a plasma nitridation process; forming a first recess in the exposed active region; and forming a stress generation layer in the first recess.

Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括通过图案化形成在包括有源区和器件隔离区的衬底上的蚀刻防止层来暴露有源区和器件隔离区; 通过进行等离子体氮化处理使暴露的器件隔离区域的上表面硝化; 在所述暴露的有源区中形成第一凹部; 以及在所述第一凹部中形成应力产生层。

公开(公告)号：KR1020140036823A

公开(公告)日：2014-03-26

申请号：KR1020120103418

申请日：2012-09-18

Applicant: 삼성전자주식회사

Inventor： 백재직 ,  차지훈 ,  윤보언 ,  이광욱 ,  한정남

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/66636

Abstract: Provided is a method for manufacturing a semiconductor device capable of simplifying a process without a loading effect by forming recesses in both sides of a gate pattern by using wet etching in a process for forming the recesses. The process for forming the recesses is performed before forming an embedded source/drain which is one of strained Si processes. The method for manufacturing the semiconductor device comprises forming a gate pattern on a substrate and forming a first recess on one side of the gate pattern through first wet etching. Etchant used in the first wet etching comprises ammonium hydroxide and hydrogen peroxide. The concentration of the hydrogen peroxide is one and a half times less than the concentration of the ammonium hydroxide.

Abstract translation: 提供一种半导体器件的制造方法，其能够通过在形成凹部的工艺中使用湿蚀刻在栅极图案的两侧形成凹陷来简化无负载效应的工艺。 在形成作为应变Si工艺之一的嵌入式源极/漏极之前进行用于形成凹部的工艺。 半导体器件的制造方法包括在衬底上形成栅极图案，并通过第一湿蚀刻在栅极图案的一侧上形成第一凹槽。 在第一湿蚀刻中使用的蚀刻剂包括氢氧化铵和过氧化氢。 过氧化氢的浓度比氢氧化铵浓度小1.5倍。

公开(公告)号：KR1020130038603A

公开(公告)日：2013-04-18

申请号：KR1020110103048

申请日：2011-10-10

Applicant: 삼성전자주식회사

Inventor： 차지훈 ,  백재직 ,  윤보언 ,  한정남 ,  안경진

IPC: H01L43/08 ,  H01L27/115 ,  H01L21/8246

CPC classification number: H01L43/08 ,  G11C13/0004 ,  H01L27/222 ,  H01L43/12

Abstract: PURPOSE: A method for manufacturing a magnetic memory device is provided to prevent the generation of an electrical short circuit due to the redeposition of etch residues on an upper magnetic pattern and a lower magnetic pattern wall. CONSTITUTION: A lower magnetic layer and an insulating layer are successively formed on a substrate(100). An upper magnetic pattern(145) is formed on the insulating layer. A main sacrificial layer(190) is formed on the sidewall of the upper magnetic pattern. The insulating layer and the lower magnetic layer are patterned to form an insulating pattern(135) and a lower part magnetic pattern(125). The main sacrificial layer is removed.

Abstract translation: 目的：提供一种用于制造磁存储器件的方法，以防止由于在上磁性图案和下磁性图案壁上的蚀刻残留物的再沉积而产生电短路。 构成：在基板（100）上依次形成下磁性层和绝缘层。 在绝缘层上形成上部磁性图案（145）。 主牺牲层（190）形成在上磁性图案的侧壁上。 图案化绝缘层和下磁性层以形成绝缘图案（135）和下部磁图案（125）。 主牺牲层被去除。

公开(公告)号：KR1020120019214A

公开(公告)日：2012-03-06

申请号：KR1020100082485

申请日：2010-08-25

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  한정남 ,  백재직 ,  조병권

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848 ,  H01L21/28255

Abstract: PURPOSE: A semiconductor integrated circuit device is provided to improve driving performance of a transistor by forming an epitaxial layer. CONSTITUTION: A gate structure including a gate dielectric layer(110) and a gate electrode(120) is formed on a substrate(100). A first sidewall spacer(130) is formed on both sidewalls of the gate structure. A second sidewall spacer(140) is formed on the first sidewall spacer. A recess compensating layer(170) is formed between the second sidewall spacer and the substrate. An epitaxial layer(180) is contacted with the recess compensating layer.

Abstract translation: 目的：提供半导体集成电路器件，以通过形成外延层来改善晶体管的驱动性能。 构成：在基板（100）上形成包括栅极介电层（110）和栅电极（120）的栅极结构。 第一侧壁间隔件（130）形成在栅极结构的两个侧壁上。 第二侧壁间隔件（140）形成在第一侧壁间隔件上。 凹陷补偿层（170）形成在第二侧壁间隔物和基底之间。 外延层（180）与凹陷补偿层接触。

公开(公告)号：KR1020090038590A

公开(公告)日：2009-04-21

申请号：KR1020070103959

申请日：2007-10-16

Applicant: 동우 화인켐 주식회사 ,  삼성전자주식회사

Inventor： 이효산 ,  윤보언 ,  이근택 ,  강대혁 ,  한정남 ,  명중재 ,  홍형표 ,  홍헌표

IPC: G03F7/34 ,  G03F7/32

CPC classification number: G03F7/425 ,  G03F1/103 ,  G03F7/063 ,  G03F7/30 ,  G03F7/32 ,  G03F7/34 ,  G03F7/422

Abstract: A photoresist stripper composition and a process of stripping photoresist by using the same are provided to cure or strip photoresist changed into a polymer after ion injection process and high temperature etching. A photoresist stripper composition comprises a mixture of sulfuric acid solution and hydrogen peroxide solution in which the weight ratio of pure sulfuric acid and pure hydrogen peroxide is 1~10,000:1; and an ammonium salt compound. The ammonium salt compound is a mixture of at least one or two selected from the group consisting of ammonium phosphate, ammonium sulfate, ammonium nitrate, ammonium borate, ammonium persulfate, ammonium citrate, ammonium oxalate, ammonium formate and ammonium carbonate.

Abstract translation: 提供光致抗蚀剂剥离剂组合物和通过使用其来剥离光致抗蚀剂的方法以在离子注入工艺和高温蚀刻之后固化或剥离变成聚合物的光致抗蚀剂。 光致抗蚀剂组合物包括硫酸溶液和过氧化氢溶液的混合物，其中纯硫酸和纯过氧化氢的重量比为1〜10,000:1; 和铵盐化合物。 铵盐化合物是选自磷酸铵，硫酸铵，硝酸铵，硼酸铵，过硫酸铵，柠檬酸铵，草酸铵，甲酸铵和碳酸铵中的至少一种或两种以上的混合物。

公开(公告)号：KR1020070113096A

公开(公告)日：2007-11-28

申请号：KR1020070001514

申请日：2007-01-05

Applicant: 삼성전자주식회사 ,  부경대학교 산학협력단

Inventor： 이효산 ,  홍창기 ,  이근택 ,  한정남 ,  오정민 ,  심우관 ,  임권택 ,  황하수 ,  할디랄유바라즈 ,  정재목

IPC: H01L21/302

Abstract: An etching, cleaning and drying method using supercritical fluid is provided to eliminate etch byproducts while preventing a lower electrode from collapsing in a process for fabricating a capacitor constituting a memory cell of a DRAM device. A material is formed(S10). The material layer is etched by using supercritical carbon dioxide in which etching chemical is melted(S11). Etch byproducts generated from a reaction of the material layer and the etch chemical are eliminated by using supercritical carbon dioxide in which cleaning chemical is melted(S12). The process for etching the material layer and the process for removing the etch byproducts can be continuously performed in the same process chamber in a critical point of carbon dioxide or higher.

Abstract translation: 提供了使用超临界流体的蚀刻，清洁和干燥方法以消除蚀刻副产物，同时防止在用于制造构成DRAM器件的存储器单元的电容器的制造工艺中下电极塌缩。 形成材料（S10）。 通过使用其中蚀刻化学品熔化的超临界二氧化碳蚀刻材料层（S11）。 通过使用其中清洗化学品熔化的超临界二氧化碳来消除由材料层和蚀刻化学品的反应产生的蚀刻副产物（S12）。 用于蚀刻材料层的方法和用于除去蚀刻副产物的方法可以在二氧化碳或更高的临界点的相同处理室中连续进行。